• Journal of KIISE:Databases
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• v.27 no.4
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• pp.549-561
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• 2000

In database management systems(DBMSs), partial rollback is a useful facility that cancels part of the executed operations upon user's requests without a total rollback. Many relational DBMSs(RDBMSs) provide this facility, However, object-orientccd DBMSs (OODBMSs) cannot utilize the previous recovery scl18lne of partial rollback usccd in (RDBMSs) since, unlike RDBMSs, they use a dual buffer consisting of an object buffer and a page buffer. Therefore, a new recovery scheme is required that rolls back the data efficiently in the dual buffer. We propose four partial rollback schemes in OODBMSs that use a dual buffer. We classify the proposed schemes into the single buffer based partial rollback scheme and the dual buffer based partial rollback scheme according to the number of buffers used for partial rollback processing. We further classify them into Uthe page buffer based partial rollback scheme, 2)the object buffccr based partial rollback scheme, 3)the dual buffer based partial rollback scheme using soft log, and 4)the dual buffer based partial rollback scheme using shadows. We evaluate the performance by mathematical analysis and experiments. The results show that the dual buffer based partial rollback scheme using shadows provides the best performance.

• Progress in Superconductivity and Cryogenics
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• v.8 no.4
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• pp.8-11
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• 2006

High temperature superconducting coated conductor has various buffer structures on Ni-W alloy. We comparatively studied the growth conditions of a multi buffer layer $(CeO_2/YSZ/CeO_2)$ and a single buffer layer$(CeO_2)$ on textured Ni-W alloy tapes. XRD data showed that the qualities of in-plane and out-of-plane textures of the two type buffer structures were good. Also, we investigated the properties of SmBCO superconducting layer that was deposited on the two type buffer structure. The SmBCO superconducting properties on the single and multi buffer structure showed different critical current values and surface morphologies. FWHM of In-plane and out-of-plane textures were $7.4^{\circ},\;5.0^{\circ}$ in the top CeO2 layer of the multi-buffer layers of $CeO_2/YSZ/CeO_2$, and $7.3^{\circ},\;5.1^{\circ}$ in the $CeO_2$ single buffer layer. $1{\mu}m-thick$ SmBCO superconducting layers were deposited on two type buffer layer. $I_c$ of SmBCO deposited on single and multi buffer were 90 A/cm, 150 A/cm and corresponding $J_c$ were $0.9MA/cm^2,\;1.5MA/cm^2$ at 77K in self-field, respectively.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1512-1515
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• 1987

The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.261-262
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• 2006

High temperature superconducting coated conductor has multi-layer structure of protecting layer/superconducting layer/buffer layer/metallic substrate. The buffer layer consists of multi layer, and the architecture most widely used in RABiTS approach is $CeO_2$(cap layer)/YSZ(diffusion barrier layer)/$CeO_2$(seed layer). Multi-buffer layer deposition required many times and process. Therefore single buffer layer deposition study reduce 2G HTS manufacture efforts. Evaporation technique for single buffer deposition method is used for the $CeO_2$ layer. $CeO_2$ single buffer film could be achieved in the chamber. Detailed deposition conditions (temperature and partial gas pressure of deposition) were investigated for the rapid growth of high quality $CeO_2$ single buffer film.

• Journal of the Semiconductor & Display Technology
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• v.3 no.3
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• pp.11-17
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• 2004

This research has been progressed for adhesive improvement of the Polyimide/Buffer layer/Cu at the COF(Chip On Film) which induced as the alternative plan about high concentration of a circuit or substrates according to demands of miniaturization and high efficiency of various electronic equipment. RF plasma equipment was applied to when plama pretreatment was performed for improvement of adhesive strength of PI and Cr as the buffer layer. Experimental fluents were a species of the buffer layer, depositied time and the ratio of $O_2$/Ar when performed to plasma pretreatment. The results are that Ni was superior to Cr at peel test according to a species of the buffer layer, peel strength and Cu THK were showed proportional relation to deposition structure of the same buffer layer and sample of the Cr depositied time(30 sec) and Cu depositied time(20 min) was showed good adhesion to peel test according to Cr's depositied time and Cu's depositied time. When perform PI's plasma pretreatment peel strength and $O_2$/Ar ratio were showed proportional relation. But $O_2$/Ar(2/5) was best condition since then decreased.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2116-2120
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• 2003

A frame buffer device is an abstraction for the graphic hardware. It allows application software to access the graphic hardware through a well-defined interface, so that the software doesn’t need to know anything about the low-level interface stuff. We develop a frame buffer driver for VIA’s CLE266 graphic system based on ‘Qplus’, an embedded linux operating system developed by ETRI. Then, it will be seen that our frame buffer system is applied to embedded solutions such as movie player and X server successfully.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.11a
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• pp.306-307
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• 2015

유기태양전지의 대표적 Hole Transporting Layer(HTL)로는 전도성 고분자인 PEDOT:PSS이다. PEDOT:PSS는 약산성의 물질로 전극을 부식시켜 디바이스의 효율을 감소시키기 때문에 PEDOT:PSS를 대체하기 위한 Buffer층에 대한 연구가 활발히 진행되어지고 있다. PEDOT:PSS를 대체할 수 있는 Nickel Oxide(NiO) Buffer 층은 wide band-gab으로 Hole Transporting Layer와 Electron Blocking Layer 역할을 동시에 하여 디바이스의 효율을 향상시킬 수 있으며, 디바이스의 수명을 향상시킬 수 있다는 장점이 있다. NiO는 용액공정과 Sputter 증착 방법으로 형성할 수 있는데, 용액공정은 고온공정이 요구되어지고 Sputter 증착방법은 산화되기 쉬운 전극위에서는 전극의 손상을 발생한다. 본 연구에서는 이러한 단점을 해결하기 위해서 Ni을 Magnetron Sputter로 증착한 후 Ion Beam 처리를 통해 산화시켜 NiO 층을 형성하는 방법을 연구하였다. 본 연구에서 제안한 NiO형성 방법으로 유기태양전지를 제작하여 PEDOT:PSS를 Buffer층으로 사용한 태양전지와 Voc가 0.72 V로 유사하게 나와 NiO가 Buffer층으로 잘 형성된 것을 확인하였다.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.564-569
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• 2002

Heteroepitaxial GaN films were grown on sapphire substrates in order to study the effects of the buffer layer's surface roughness and thermal treatment on the epitaxial layer's quality. For this, GaN buffer layers were grown at $550^{\circ}C$ with various TMGa flow rates and durations of growth, and annealed at $1010^{\circ}C$ for 3 min after the temperature was raised by 23 ~ $92^{\circ}C/min$, and then GaN epitaxial layers were grown at $1000^{\circ}C$. It has been found that the buffer layer's surface roughness and the thermal treatment condition are critical factors on the quality of the epitaxial layer. When a buffer layer was frown with a TMGa flow rate of $24\mu mole/min$ for 30 sec, the surface roughness of the buffer lather was minimum and when the thermal ramping rate was $30.6^{\circ}C/min$ on this layer, the successively grown epitaxial layer's crystalline and optical qualities were optimized with a specular morphology. The minimum full width at half maximum(FWHM) of GaN(0002) x-ray diffraction peak and that of near-band-edge(NBE) peak from a room temperature photoluminescence (PL) were 5 arcmin and 9 nm, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.240-241
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• 2007

In general, high temperature superconducting coated conductors have intermediary buffers layer consisting of seed, diffusion barrier and cap layers. Simplification of the oxide materials buffer architecture in the fabrication of high temperature superconducting coated conductors is required because the deposition of multi-layers buffer architecture leads to a longer manufacturing time and a higher cost process of coated conductors. Thus, single buffer layer deposition seems to be important for practical coated conductor manufacturing process. In this study, a single gradient layered buffer deposition process of YZO for low cost coated conductors has been tried using DC reactive sputtering technique. About several thick YZO gradient single buffer layers deposited by DC co-sputtering process were found to act as a diffusion layer.