• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2310-2316
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• 2010

This paper presents an application of retiming to model checking, a branch of formal verification. Retiming can change the transition relation of a circuit without changing its input-output behaviour by relocating its registers. With the retiming, a given circuit can have a different structure more adequate for model checking. This paper proposes a cost function to reflect the number of registers and the characteristic of its transition relation and develops a heuristic annealing algorithm to search efficiently the circuit structures obtained by retiming. Experimental results show that the proposed method can improve the model checking performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.1-7
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• 1999

In this research, transformation-based optimization techniques for pipelined designs have been developed. The transformation-based optimization techniques include pipelined architecture transformations and retiming transformations. The new transformation method has the following three features. First, the overall performance of a pipelined system is optimized owing to various transformations including retiming of multiple pipelined blocks. Second, these techniques can be used to search a large solution space by allowing efficient exploration of trade-offs between area and performance. Third, these techniques can be easily extended to a new transformation or algorithm and can be used to optimize memory or bus architectures. Experimental results illustrate that these transformation-based optimization techniques improve area by 21% and performance by 17% on the average for a set of pipelined designs. Especially, the techniques are useful to efficiently explore a large design space.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.29-34
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• 2016

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• ETRI Journal
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• v.34 no.3
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• pp.352-360
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• 2012

This paper proposes a low-cost, low-power, and high-capacity optical-electrical-optical-type reach extender that can provide 3R frame regeneration and remote management to increase the reach and split ratio with no change to a legacy time division multiple access passive optical network. To provide remote management, the extender gathers information regarding optical transceivers and link status per port and then transmits to a service provider using a simple network management protocol agent. The extender can also apply to an Ethernet passive optical network (E-PON) or a gigabit-capable PON (G-PON) by remote control. In a G-PON, in particular, it can provide burst mode signal retiming and burst-to-continuous mode conversion at the upstream path through a G-PON transmission convergence frame adaptor. Our proposed reach extender is based on the quad-port architecture for cost-effective design and can accommodate both the physical reach of 60 km and the 512 split ratios in a G-PON and the physical reach of 80 km and the 256 split ratios in an E-PON.

• Proceedings of the Optical Society of Korea Conference
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• 2002.07a
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• pp.154-155
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• 2002

완전 광 3R(Retiming, Reshaping, Reamplification) 재생기는 WDM 시스템과 광 네트워크의 크기를 확장시키기 위하여 필요한 매우 중요한 소자이다. 완전 광 3R 재생기의 구현에서 입력 광 신호로부터 광 클락 추출은 가장 핵심적인 요소이다. 이러한 광 클락 추출을 위하여 모드락 레이저 다이오드와 다중 전극 DFB 레이저에서 self-pulsating 현상을 이용하는 방법이 많이 연구되고 있다. 독일의 HHI는 다중 전극 DFB 레이저에서 self-pulsating 현상을 이용하여 80 GHz 초고속 광 클락 추출과 25-82 GHz 전기적 튜닝 특성을 보였다. (중략)

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.69-77
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• 2005

The Viterbi decoder which is used for the forward error correction(FEC) is a crucial component for successful modern communication systems. As modern communication speed rapidly high, the development of high speed communication module is important. However, since the feedback loop in ACS operation, high speed of Viterbi decoder is very difficult. In this paper, we propose an area reduced, high speed ACS Architecture of Viterbi decoder based on the radix-4 architecture. The area is reduced by rearranging the ACS operations, and the speed is improved by retiming of path metric memory. The proposed ACS architecture of Viterbi decoder is implemented in VHDL and synthesized in Xilinx ISE 6.2i. The area-time product of the proposed architecture is improved by 11% compared to that of the previous high speed radix-4 ACS architecture.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2528-2535
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• 2000

Technology mapping is a part of VLSI CAD system, where circuits in logical level are mapped into circuits in physical level. The performance of technology mapping system is evaluatecJ by the delay and area of the resulting circuits. In the sequential circuits, the delay of the circuit is decided by the maximal delay between registers. In this work, we introduce an FPGA mapping algorithm improved by retiming technique used in constructive level and iterative level, and by fuzzy logic technique. Initial circuit is mapped into an FPGA circuit by constructive manner and improved by iterative retiming. Criteria given to the initial circuit are structured hierarchically by decision-making functions of fuzzy logic. The proposed system shows better results than previous systems by the experiments with MCNC benchmarkers.