The Transactions of the Korea Information Processing Society (한국정보처리학회논문지)

Korea Information Processing Society (한국정보처리학회)
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Efficient Technology Mapping of FPGA Circuits Using Fuzzy Logic Technique

퍼지이론을 이용한 FPGA회로의 효율적인 테크놀로지 매핑

  • Lee, Jun-Yong (Dept. of Computer Engineering, Hongik University) ;
  • Park, Do-Soon (Dept. of Computer Engineering, Hongik University)
  • 이준용 (홍익대학교 컴퓨터공학과) ;
  • 박도순 (홍익대학교 컴퓨터공학과)
  • Published : 2000.08.01
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Abstract

Technology mapping is a part of VLSI CAD system, where circuits in logical level are mapped into circuits in physical level. The performance of technology mapping system is evaluatecJ by the delay and area of the resulting circuits. In the sequential circuits, the delay of the circuit is decided by the maximal delay between registers. In this work, we introduce an FPGA mapping algorithm improved by retiming technique used in constructive level and iterative level, and by fuzzy logic technique. Initial circuit is mapped into an FPGA circuit by constructive manner and improved by iterative retiming. Criteria given to the initial circuit are structured hierarchically by decision-making functions of fuzzy logic. The proposed system shows better results than previous systems by the experiments with MCNC benchmarkers.

테크놀로지 매핑은 VLSI 설계자동화(CAD) 시스템의 한 단계로서, 설계된 회로를 논리적 단계에서 물리적 단계로 매핑해 준다. 테크놀로지 매핑은 효율성은 매핑된 회로의 자연시간과 회로의 면적에 의해서 평가되어진다. 특히 순차회로에서는 레지스터 사이의 조합회로의 최대지연시간에 의해서 전체회로이 지연시간이 결정된다. 본 논문에서는 순차회로에 대한, 건설적인(constructive) 단계와 반복적인(iterative)단계의 리타이밍 기술과 퍼지 논리에 의해 향상된 FPGA 매핑 알고리즘을 소개한다. 주어진 초기회로는 건설적인 방법에 의하여 FPGA회로로 초기매칭 되어진 후 반복적인 리타이밍에 의하여 매핑회로의 효율을 높이게된다. 초기회로에 주어진 여러 가지 기준들을 결정 함수(Decision Marking Function)에 대한 퍼지 이론 규칙의 계층적인 구조로 구성된다. 제안된 매퍼는 MCNC 밴치마커의 실험을 통해 지연시간과 면적에서 기존 매핑시스템의 성능을 능가함을 보여준다.

Keywords

References

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