• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5B
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• pp.286-294
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• 2007

In ASIP design, compiler is required for performance evaluation of processors being designed. The design of machine specific compiler is time consuming. This paper presents the system which generates C compiler from MDL descriptions. Compiler generation using MDL can support user retargetability and concurrency between compiler design and processor design. However, it must overcome semantics gap between compiler and machine. To handle this problem, the proposed system maps behavioral descriptions to library which contains abstract behavior for each tree pattern. Using mapped instructions and information on register file usage, the proposed system generates back-end interface function of the compiler. Generated compilers, for MIPS R3000, ARM9 cores, have been proved by application programs written in C code.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.431-434
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• 2003

과거 임베디드 시스템은 산업용 같은 특수한 경우와 여러 전자 제품에서 눈에 뛰지 않는 형태로 사용이 되어 왔지만 최근 들어 정보통신 분야가 발전하고 가격 대 성능비가 우수한 Microcontroller 와 CPU 들이 등장하면서 더욱 더 각광을 받기 시작했다. 이들의 개발환경은 C 언어와 어셈블리어가 주를 차지하고 있는데 개발상의 많은 장점 때문에 C 언어를 선택하여 사용하고 있지만 target machine 의 C 컴파일러가 전부 제공되지 않고 일부 machine 만 제공되고 있기 때문에 C 언어의 사용은 아직 제한적이다. 이에 본 논문에서는 Retargetable Compiler 인 LCC 를 이용하여 임베디드용 machine 에 대해 retargeting 이 가능하도록 LCC 를 개선시키고자 한다.

• The KIPS Transactions:PartA
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• v.16A no.4
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• pp.245-254
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• 2009

With the increasing adoption of embedded processors, the need of developing compilers for the embedded processors with timely manner is also growing. Retargeting has been adopted as a viable approach to constructing new compilers by modifying the back-end of an existing compiler. This paper proposes a test suite generation system for testing retargetable C compilers. The proposed system generates the test suite using the grammar coverage concept. Generally, the size of the test suite satisfying the grammar coverage of the source language is very large. Hence, the proposed system also provides the facility to reduce the size of the test suite. According to the experimental result, the reduced test suite can detect 75% of the compiler faults detected by the original test suite though the size of the reduced test suite is only 10% of that of the original test suite in average. This result indicates that the reduction technique proposed in this paper can be effectively used in the prior phase of the development procedure of the embedded compilers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.913-921
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• 2007

Retargetable compiler which generates executable code for a target processor and performance profiler are required to design a processor optimized for a specific application. This paper presents an architecture exploration methodology based on ADL (Architecture Description Language). We synthesized instruction set and optimized processor structure using information extracted from application program. The information of operation sequences executed frequently and register usage are used for processor optimization. Architecture exploration has been performed for JPEG encoder to show the effectiveness of the system. The ASIP designed using the proposed method shows 1.97 times better performance.