• East Asian mathematical journal
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• v.31 no.2
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• pp.211-244
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• 2015

The arithmetic operation have double-sided character. One is calculation as a process, the other is understanding in results as an outcome of the operation. We harbored suspicion on students' misunderstanding in an outcome of the operation, because the curriculum has focused on the calculation, as a process of arithmetic operation. This study starts with the presentation of this problem, we tried to find the recognition ability and character in the arithmetic operation. We researched the recognition ability for 7th grade 27 students who have enough experience in arithmetic operation when studying in elementary school. And we had an interview with 3students individually, that has an error in understanding in results of arithmetic operation but has no error in calculation. We focused on 3students' detailed appearance of the ability to understand in results of arithmetic operation and analysed the changing appearance after recommending unit record using operation expression. As a result, we could find the abily to underatanding in results of arithmetic operation and applicability to recommend unit record using operation expression. Through these results, we suggested educational implications in understanding in results of arithmetic operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• 한국데이터정보과학회:학술대회논문집
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• 2006.11a
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• pp.81-95
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• 2006

The usual arithmetic operations on real numbers can be extended to arithmetical operations on fuzzy intervals by means of Zadeh's extension principle based on a t-norm T. A t-norm is called consistent with respect to a class of fuzzy intervals for some arithmetic operation if this arithmetic operation is closed for this class. It is important to know which t-norms are consistent with a particular type of fuzzy intervals. Recently Dombi and Gyorbiro proved that addition is closed if the Dombi t-norm is used with two bell-shaped fuzzy intervals. A result proved by Mesiar on a strict t-norm based shape preserving additions of LR-fuzzy intervals with unbounded support is recalled. As applications, we define a broader class of bell-shaped fuzzy intervals. Then we study t-norms which are consistent with these particular types of fuzzy intervals. Dombi and Gyorbiro's results are special cases of the results described in this paper.

• East Asian mathematical journal
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• v.38 no.2
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• pp.257-275
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• 2022

Recently, there are studies the argument that arithmetic rules established by the four fundamental arithmetic operations, in other words, commutative laws, associative laws, distributive laws, should be explicitly described in mathematics textbooks and the curriculum. These rules are currently implicitly presented or omitted from textbooks, but they contain important principles that foster mathematical thinking. This study aims to evaluate the current level of understanding of these computation rules and provide implications for the curriculum and textbook writing. To this end, the correct answer ratio of the five arithmetic rules for 1-4 grades 398 in five elementary schools was investigated and the type of error was analyzed and presented, and the subject to learn these rules and the points to be noted in teaching and learning were also presented. These results will help to clarify the achievement criteria and learning contents of the calculation rules, which were implicitly presented in existing national textbooks, in a new 2022 revised curriculum.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.185-191
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• 2018

This study examined the type and extent of interruption between induced emotion and succeeding arithmetic operation. The experiment was carried out to determine the influence of the induced emotions (anger, joy, and sorrow) and stimulus types (picture and sentence) on the cognitive process load that may block the interactions among the constituents of working memory. The study subjects were 32 undergraduates who were similar with respect to age and education parameters and were especially instructed to attend to induced emotion by imitation of facial expression and to make a correct decision during the remainder calculation task. In the results, the stimulus types did not exhibit any difference but there was a significant difference among the induced emotion types. The difference was observed in slower response time at positive emotion(joy condition) as compared with other emotions(anger and sorrow). More specifically, error and delayed correct response rate for emotion types were analysed to determine which phase the slower response was associated with. Delayed responses of the joy condition by sentence-inducing stimulus were identified with the error rate difference, and those by picture-inducing stimulus with the delayed correct response rate. These findings not only suggest that induced positive emotion increased response time compared to negative emotions, but also imply that picture-inducing stimulus easily affords arithmetic fluctuation whereas sentence-inducing stimulus results in arithmetic failure.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Korean Data and Information Science Society
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• v.13 no.2
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• pp.209-216
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• 2002

In this paper, we introduce a concept of (H)-property which generalize that of increasing(decreasing) property of binary operation. We also treat some works related to operations on fuzzy numbers and generalize earlier results of Kawaguchi and Da-te(1994).