• Journal of the Korea institute for structural maintenance and inspection
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• v.15 no.3
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• pp.116-124
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• 2011

In this study, a new method to estimate the bridge deflection is developed by using Wireless Tilt Sensor. Most of evaluations of structural integrity, it is very important to measure the geometric profile, which is a major factor representing the global behavior of civil structure, especially bridges. In the past, Because of the lack of appropriate methods to measure the deflection curve of bridges on site, the measurement of deflection had been done restrictly within just a few discrete points along the bridge. Also the measurement point could be limited to locations installed with displacement transducers. So, in this study, the deflection of the structure was measured by wireless tilt sensor instead of LVDT(Linear Variable Differential Transformer). Angle change of tilt sensor shows structural behavior by the change of the resistor values which is presented to voltage. Moreover, the maximum deflection was calculated by changing the deflection angle which was calculated as V(measured voltage) ${\times}$F(factor) to deflection. The experimental tests were carried out to verify the developed deflection estimation techniques. Because the base of tilt measuring is the gravity, uniform measurement is possible independent of a measuring point. Also, measuring values were showed very high accuracy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.1
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• pp.40-45
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• 2015

Electrode systems: a protrusion on conductor (POC), a protrusion on enclosure (POE), a crack in epoxy plate and a free particle (FP) were fabricated to simulate insulation defects in a gas insulated switchgear (GIS). $SF_6$ gas was filled in the electrode systems by 3 bar and/or 5 bar, respectively. Partial discharge (PD) pulses were detected through a $50{\Omega}$ non-inductive resistor. A calibration test was carried out according to IEC 60270, and the sensitivity was 0.25 pC/mV. PD pulses were distributed in the phase of $50^{\circ}{\sim}135^{\circ}$ and over 95% of them existed in the phase of $55^{\circ}{\sim}120^{\circ}$ for the POC. PD pulses were distributed in the phase of $230^{\circ}{\sim}310^{\circ}$ and over 90% of them existed in phase of $220^{\circ}{\sim}300^{\circ}$ for the POE. PD pulses occurred in the phase of $40^{\circ}{\sim}60^{\circ}$ and $220^{\circ}{\sim}300^{\circ}$ for the crack, and pulse counts were 25% higher in negative polarity than in positive polarity. PD pulses were distributed in every phase unlike to other three electrode systems and the peak magnitude was measured at $118^{\circ}$ and $260^{\circ}$ for the FP. As described above, PD pulses were observed in positive polarity for the POC, in negative one for the POE, in both one for the crack and the FP. In conclusion, it is expected that the identification rate of defect type can be improved by considering the polarity ratio of PD pulses on the PRPDA method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.6
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• pp.34-42
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• 2002

In this paper, we propose a temperature independent the detective voltage source in voltage detector. The value of a detective voltage source is designed to become m times of silicon bandgap voltage at zero absolute temperature. By properly choosing the temperature coefficient of diode, the temperature coefficient of a concave voltage nonlinearities generated by the ${\Delta}V_{BE}$ section of diode between base and emitter of transistors with a different area can be summed with convex nonlinearities the $V_{BE}$ voltage to achieve the near zero temperature coefficient of the detective voltage source. We designed that the value of a detective voltage can be varied by ${\Delta}V_{BE}$, the $V_{BE}$multiplier circuit and resistor. In order to verify the performance of a proposed detective voltage source, we manufactured the voltage detector IC for 1.9V which is fabricated in $6{\mu}m$ Bipolar technology and measured the operating characteristics, the temperature coefficient of a detective voltage. To reduce the deviation of a detective voltage in the IC process step, we introduced a trimming technology, ion implantation and an isotropic etching. In manufactured IC, the detective voltage source could achieve the stable temperature coefficient of 29ppm/$^{\circ}C$ over the temperature range of -30$^{\circ}C$ to 70$^{\circ}C$. The current consumption of a voltage detector constituted by the proposed detective voltage source is $10{\mu}A$ from 1.9V-supply voltage at room temperature.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.90-95
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• 2014

This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.651-658
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• 2001

A novel multi-section power divider configuration is proposed to obtain wide-band frequency performance up to microwave frequency region. Design procedures for the proposed microwave broadband power divider are composed of a planar multi-section three-ports hybrid and a waveguide transformer design procedures. The multi-section power divider is based on design theory of the optimum quarter-wave transformer. Furthermore, in order to obtain the broadband isolation performance between the two adjacent output ports, the odd mode equivalent circuit should be matched by using the lossy element such as resistor. The derived design formula for calculating these odd mode matching elements is based on the singly terminated filter design theory. The waveguide transformer section is designed to suppress the propagation of the higher order modes such as waveguide modes due to employing the metallic electric wall. Thus, each section of the designed waveguide transformer should be operated with evanescent mode over the whole design frequency band of the proposed microwave broadband power divider. This paper presents several simulations and experimental results of multi-section power divider to show validity of the proposed microwave broadband power divider configuration. Simulation and experiment show excellent performance of multi section power divider.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1223-1229
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• 2004

A variable-gain low-voltage low noise amplifier MMIC operating at 5GHz frequency band is designed and implemented using the ETRI 0.5$\mu\textrm{m}$ GaAs MESFET library process. This low noise amplifier is designed to have the variable gain for adaptive antenna array combined in HIPERLAN/2. The feedback circuit of a resistor and channel resistance controlled by the gate voltage of enhancement MESFET is proposed for the variable-gain low noise amplifier consisted of cascaded two stages. The fabricated variable gain amplifier exhibits 5.5GHz center frequency, 14.7dB small signal gain, 10.6dB input return loss, 10.7dB output return loss, 14.4dB variable gain, and 2.98dB noise figure at V$\_$DD/=1.5V, V$\_$GGl/=0.4V, and V$\_$GG2/=0.5V. This low noise amplifier also shows-19.7dBm input PldB, -10dBm IIP3, 52.6dB SFDR, and 9.5mW power consumption.

• The korean journal of orthodontics
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• v.18 no.1 s.25
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• pp.189-207
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• 1988

In almost all biologic systems, mechanically induced electric charge separation is a fundamental phenomenon. Since the hypothesis was established that the generation of electric potentials in bone by mechanical stress including muscular force might control the activity in bone by mechanical stress including muscular force might control the activity of osseous cells and their biopolymeric byproduct, the concept of electrically mediate growth mechanism, which involves biological growth and bone remodeling by any means, in living systems has been applied clinically and experimentally to orthopedic fracture repair, the regulation of orthodontic tooth movement, epiphyseal cartilage regeneration, etc. On the other hand, recent numerous research data available show apparently that the mandibular condyle has the characteristics of growth center as well as growth site. In addition, there exists a considerable difference of opinion as to the role of external pterygoid muscle in condylar growth. In view of these evidences, this. experiment was performed to investigate the effect of the galavic current on the growth of the mandible and condyle for elucidating the nature of condylar growth. The bimetallic device was composed of silver and platinum electrode connected with resistor (3.9 Mohm), which was expected to produce galvanic current of 23.6 nA according to the galvanic principle. The 25 Sprague-Dawley rats were divided into two group, 2 week group comprising 8 animals exposed to satanic current for 2 weeks and 3 control animals not exposed for 2 weeks, 4 week group comprising 10 animals in experimental group and 4 animals in control group applied for 4 weeks respectively. The experimental rats were subjected to application of the galvanic current invasively to codylar head surface and the control groups with sham electrode. On the basis of anatomic and histologic data from the mandibular condyle of experimental and control group, the following results were obtained. 1. After 2 weeks, there was no increase of mandibular size in experimental group over that of the control group. 2. After 4 weeks, the size of the condylar head was larger in experimental group than that of the control. 3. In 2 week group, the thickness of the mitotic compartment and hypertrophic chondroblastic layer was increased in experimental group. 4. In 4 week group, the number and the size of the hypertrophic chondroblasts were increased significantly on experimental group over that of the control group. 5. The application of the satanic current caused an increase in chondrocytic hypertrophy and intercellular matrix in both groups.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.