• 한국산학기술학회논문지
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• 제8권4호
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• pp.743-747
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• 2007

반도체 소자 제작에 있어서 회로의 pattern 형성에 이용하는 차세대 lithography 공정 기술을 위해서 전자빔 lithography 공정 기술 연구가 진행되고 있다. 본 연구에서는 Gauss 해석법과 Monte Carlo의 수치해석법을 사용하여 두께 100 nm의 PMMA (poly-methyl-methacrylate) resist에 전자 $1{\times}10^4$를 입사시키고, 입사 전자빔 에너지에 따른 PMMA 내에서의 투과 깊이를 비교하였다. 전자빔 에너지의 크기는 100eV, 300eV, 500eV, 700eV, 그리고 1000eV에 대하여 simulation을 실시하였다.

• 한국표면공학회지
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• 제29권6호
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• pp.869-875
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• 1996

In this article the effects of process parameters of inductively coupled plasma etching with $SF_6$ /$N_2$/Ar mixture gas and mask materials on the etched profile of W were investigated. While the etched profile was improved by $N_2$-addition, low working presure, and reduced $SF_6$ flow rate, the etching selectity (W against SAL resist) was decreased. Due to the difficulty of W etching with single layer resist, sputter deposited $Al_2O_3$ film was used as a hardmask. Reduction of required EB resist thickness through $Al_2O_3$ mask application could reduce proximity effect during e-beam patterning, but the etch anisotropy was degraded by decreased sidewall passiviation effect.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 춘계학술대회 논문요약집
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• pp.126-126
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• 2004

1996년 Chou 등이 개발한 가열방식의 나노임프린트 리소그래피(nanoimprint lithography, NIL)은 선폭 100nm 이하의 나노구조물을 경제적으로 제작할 수 있는 대표적인 나노패턴닝(nano-patterning) 공정으로 많은 기대가 모아지고 있으나, 열변형에 의해 다층정렬이 어렵다는 점과, 점도가 큰 레지스트(resist)를 임프린트하기 위해서는 고압(∼30 bar)이 필요하다 점 등의 문제점이 있다. 이를 해결할 수 있는 방법으로 UV 나노임프린트 리소그래피(ultraviolet nanoimprint lithography, UV-NIL)를 들 수 있다.(중략)

• 분석과학
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• 제5권4호
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• pp.455-464
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• 1992

본 논문에서는 FT-IR 분광분석법을 이용하여 여러 가지 반응조건에서 기체상 silylation 반응에 의해 생성된 silylated layer의 depth를 비파괴적으로 정량하는 방법을 제안하였다. Silylated layer의 depth는 FT-IR 스펙트럼의 특성 봉우리들(Si-O-ph, Si-C, Si-H)의 흡광도를 바탕 스펙트럼 공제법으로 측정하여 SEM의 두께 측정치와 비교하여 정량하였다. FT-IR 분광분석법을 이용한 Silylated layer의 depth 분석은 비파괴적이고 정량적인 방법으로, 이 방법은 silylation process window를 설정하는 데 적합하다는 것을 알았다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1244-1247
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• 2004

For obtaining the best panel quality of color filter on array(COA) architecture in TFF LCD, we investigated the influence of deposition temperature, $O_2$ flow, thickness on the optical transmittance, wet etching and adhesion properties of IZO deposited onto each color photo resist(red, green, blue). Average transmittance of the pixel single layer in the visible range(between 380 and 780nm) was mainly affected by thickness and showed maximum at 1250 ${\AA}$ while the thickness showing peak transparency in each R, G, B wavelength was different. The relation was calculated by using bi-layer transmission and reflectance model, which corresponded to experimental data very well. The adhesion of IZO deposited on each color PR was found to have enhanced value except red PR case, compared to that of IZO which was deposited on $SiN_x$. Wet etching pattern linearity was decreased as the thickness increased. The thickness of IZO was one of vital factors in order to optimize overall pixel process for fabricating COA structure.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1419-1421
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• 1995

Nickel micro-structures are fabricated by electroless plating which shows better uniformity. Positive resist AZ4562 of 7 um thickness is patterned with minimum width of 2 um on poly-silicon as for sacrificial layer. The growth rate of Ni electroless plating is 10um/h both for the seed layer of Pt and TiW. TiW is found to be more practical than Pt, since it is very difficult to remove Pt with negligible damage to Ni structures.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.187-190
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• 1999

We have developed fabrication processes that form a wide-head T-gate with a 0.2 ${\mu}{\textrm}{m}$ gate length using the combination of thickness of each PMMA layer, line doses and development times for applications in millimeter- and micro-waves monolithic integrated circuits. The three-layer resist structure (PMMA/P(MMA-MAA)/PMMA = 1800 $\AA$/5800 A/1900$\AA$), 4nC/cm and over development were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. The experimented results show that the cross sectional area of T-gate fabricated by the proposed method is easily enlarged without additional processes.

• Journal of Welding and Joining
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• 제32권3호
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• pp.60-67
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• 2014

The ability of electronic packages and assemblies to resist solder joint failure is becoming a growing concern. This paper reports on a study of high speed shear energy of Sn-4.0wt%Ag-0.5wt%Cu (SAC405) solder with different electroless Ni-P thickness, with $HNO_3$ vapor's status, and with various pre-conditions. A high speed shear testing of solder joints was conducted to find a relationship between the thickness of Ni-P deposit and the brittle fracture in electroless Ni-P deposit/SAC405 solder interconnection. A focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the fractured pad surface with and without $HNO_3$ vapor treatment. A scanning electron microscopy (SEM) and an energy dispersive x-ray analysis (EDS) confirmed that there were three intermetallic compound (IMC) layers at the SAC405 solder joint interface: $(Ni,Cu)_3Sn_4$ layer, $(Ni,Cu)_2SnP$ layer, and $(Ni,Sn)_3P$ layer. The high speed shear energy of SAC405 solder joint with $3{\mu}m$ Ni-P deposit was found to be lower in pre-condition level#2, compared to that of $6{\mu}m$ Ni-P deposit. Results of focused ion beam and energy dispersive x-ray analysis of the fractured pad surfaces support the suggestion that the brittle fracture of $3{\mu}m$ Ni-P deposit is the result of Ni corrosion in the pre-condition level#2 and the $HNO_3$ vapor treatment.

• 마이크로전자및패키징학회지
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• 제13권2호
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• pp.1-7
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• 2006

본 논문에서는 솔더 레지스트(solder resist)의 두께와 코어의 물성에 따른 인쇄회로기판의 철의 크기와 형상에 대하여 연구하였다. 인쇄회로기판의 굽힘 변형은 적층되는 재료의 열팽창계수의 차이에 의해 발생한다. 따라서 굽힘 변형의 감소를 위해서는 열팽창계수의 차이가 작은 적층 재료를 사용하는 것이 필요하며, 구조 형상에서도 상면과 하면의 불균일성을 완화시킬 필요가 있다. 또한, 적층 재료에서 코어의 강성을 높여 점의 발생을 억제할 수 있다. 코어를 이루는 복합재료는 적층 순서와 섬유 각에 따른 물성 특성의 방향성에 따라 굽힘과 비틀림이 연성되는 현상을 보이며, 이와 같은 성질을 이용하면 휨을 제어할 수 있다. 본 연구에서는 2층으로 구성된 chip scale package (CSP) 기판의 휨에 대한 연구로, 실험 및 유한 요소해석 툴을 이용하여 개선 결과를 도출하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1214-1218
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• 2006

We introduced simple fabrication process for field emission devices based on carbon nanotubes (CNTs) emitters. Instead of using the ITO material as a transparent electrode, a metal (Au) with thickness of 5-20nm was used. Moreover, the ITO patterning process was eliminated by depositing metal layer, before the CNT printing process. In addition, the thin metal layer on photo resist (PR) layer was used as UV block. We fabricated the CNT field emission arrays of triode structure with simple process. And I-V characteristics of field emission arrays were measured. The maximum current density of $254{\mu}A/cm2$ was achieved when the gate and the anode voltage was kept 150V and 3000V, respectively. The distance between anode and cathode was kept constant.