• 대한전자공학회논문지
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• 제27권8호
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• 전자공학회논문지C
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• 제35C권2호
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• pp.1-9
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• 1998

To achieve high performance in VLIW processors, they must exploit the parallelism on application programs. Data dependency makes it difficult to find the instruction-level parallelism. Among the three kinds of data dependency, true dependency causes RAW(Read After Wirte) hazards that occur most frequently in VILW processors. Forwarding is a widely used technique to reduce the performance degradation caused by RAW hazards. However, forwarding requires too much area of the chip when it is applied to VLIW processors. In this paper, static forwarding is proposed to reduce the hardware cost of forwarding circuits. It needs an extended compiler to detect RAW hazards and control the proposed forwarding scheme via instruction. And it uses the modified register file to shrink the area of forwarding path. VLIW Processor Model is also designed to verify static forwarding. This paper describes the operation of static forwarding and the comparison with the conventional forwarding.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.597-598
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• 2008

In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

• International Journal of Advanced Culture Technology
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• 제6권3호
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• pp.193-200
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• 2018

This paper describes the design and trial development of a system that supports continuous hazard mapping by local residents in their daily life. We performed an interview survey to design our system in a model traditional town in Saga Prefecture, Japan. The results show that despite continued efforts, many practical problems remain and residents feel unsafe. Considering these results, we designed and developed a unique information and communication technology-based support system that contributes to community-based disaster prevention and reduction. The continuous resident participation and posting design are the core concept for our community-based approach. Our system continues to support making a hazard map by integrating the community-based hazard information. Local residents register information (disaster types, risk level, photographs, comments, positional information) about locations that could be dangerous in a disaster. In addition, our system enables information sharing through a Web server. We expect that this information sharing will allow local hazard information for each district to be used.

• Journal of Advanced Marine Engineering and Technology
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• 제23권1호
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• pp.62-68
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• 1999

The strength data on AlBC3 and HBsC1 which are used for materials of marine propeller blade are insufficient as used of material limited and even rules of KR(Korean Register of Shipping) describe only a point of view that the chemical composition and men values of mechanical proper-ties have to be certain level. In this study distribution characteristics as well as mean values of mechanical properties are investigated through the tensile test and the characteristics of fatigue strength are investigated through the fatigue test.

• 정보과학회지
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• 제5권2호
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• pp.94-98
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• 1987

本 論文에서는 多値論理回路를 實現함에 있어서 發生하는 Hazard를 2가 지, 卽 Function Hazard와 Logic Hazard로 分類하였고 이의 解決方案으로 入力 信號가 Switching하여 最終 安定 level에 到達했을 때 Switching函數를 決定하고 이 函數로써 Switching函數의 Unate性을 試圖하였다. 그리고 內部回路에서 信號 가 遷移될 때 內部回路의 遲延 遲延時間으로 말미암아 發生되는 Hazard狀態를 Redundant回路를 實現하였다. 또 이 論理回路를 基本으로한 N値 Flip-flop N과 Shift Register, Counter等의 順序論理回路를 構成하였다.

• 한국컴퓨터정보학회논문지
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• 제7권2호
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• pp.40-45
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• 2002

본 연구는 상위수준합성에서의 데이터패스합성을 위한 스케쥴링을 다루었다. 특히, 연산자 할당에 필요한 상호연결선을 최적화하기 위한 스케쥴링 방법을 제안하였다. 또한 최적의 스케쥴링 결과를 얻기 위하여 ILP 수식을 이용하였고 본 연구의 효용성을 검증하기 위하여 5차 디지털 웨이브 필터를 대상으로 실험한 결과 기존의 결과 보다 나은 결과를 나타내었다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2000년도 가을 학술발표논문집 Vol.27 No.2 (3)
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• pp.30-32
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• 2000

본 논문에서는 RTL 회로의 데이터패스에 대한 테스트 용이도 분석방식과 테스트 용이화 설계방식을 제안한다. 데이터패스에 대한 테스트 용이도 분석은 콘트롤러에 대한 정보없이 RTL 회로의 데이터패스만으로 수행한다. 본 논문에서 제안한 테스팅을 고려한 설계방식은 내장된 자체 테스트(BIST)나 주사(scan)방식이 아니며, 주사 방식을 적용했을 때에 비해 본 논문에서 제안한 테스트 용이화 설계방식을 적용했을 때에 보다 적은 면적 증가율(area overhead)을 보인다는 것을 실험을 통해 확인하였다. 또한, 회로 합성 후 ATPG를 통해 적은 면적 증가만으로 높은 고장 검출율(fault coverage)을 얻을 수 있음을 보인다.

• Journal of Information Technology Applications and Management
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• 제16권1호
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• pp.37-50
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• 2009

The benefits of an e-learning system will not be maximized unless learners use the system. This study proposed and tested models that seek to explain students' satisfaction withe-learning systems. A survey was performed at a women's college in Korea, where students experimentally could choose to register one same course either through e-learning or class-room learning. The questionnaire was filled up by students who took e-learning option. independent variables include expected benefits, familiarity with technology, social influence, and accessibility. Dependent variables include the level of satisfaction, academic achievement, and the amount of the use of systems.

• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.433-436
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• 2010

In this paper, we presented a ciphering method whose target data is any kind of digital bit-stream. It uses a chaotic system as the main encrypting tool, MISR (Multi-Input Signature Register), and shift-and-rotation function, all of which are exclusive-ORed with the plaintext. Also, it incorporates a cipher text feedback mode such that part of the previously ciphered data is fed back to encrypt the current data. The encryption block size and the amount of feedback data are different at each ciphering operation. Experimental results with the image/video date showed that this method has enough speed and encryption effect with negligible latency time. Thus, we are expecting it to have various application areas that need high speed stream ciphering with high security level.