• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.73-76
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• 2001

High-level synthesis generates a structural design that implements the given behavior and satisfies design constraints for area, performance, power consumption, packaging, testing and other criteria. Thus, high-level synthesis generates that register-transfer(RT) level structure from algorithm level description. High-level synthesis consist of compiling, partitioning, scheduling. In this paper, we proposed the efficient scheduling algorithm that find the number of the functional unit and scheduling into the minimum control step with silicon area resource constrained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.571-578
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• 2012

In this paper, we propose two main points. The first is the constraint for logic synthesis, and the second is an efficient logic synthesis method. Logic synthesis is a process to obtain the gate-level netlist from RTL (register transfer level) codes using logic mapping and optimization with the specified constraints. The result of logic synthesis is tightly dependent on constraint and logic synthesis method. Since the size and timing can be dramatically changed by these, we should precisely consider them. In this paper, we present the considering items in the process of logic synthesis by using our experience and experimental results. The proposed techniques was applied to a circuit with the hardware resource of about 650K gates. The synthesis time for the hybrid method was reduced by 47% comparing the bottom-up method and It has better timing property about slack than top-down method.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.561-562
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• 2008

In this paper, we propose a establishment of system level environment to exploit PC system with SSD (Solid State Disk) by using TLM (Transaction Level Modeling) method with SystemC language. The reason why we choose this modeling method is that it eases RTL (Register Transfer Level) modeling burdens and we can accurately estimate the performance about different architectural changes. Also, it provides simulation speed which is relatively faster than RTL modeling method. The baseline architectural platform we implemented showed that SSD's internal transfer time is a dominant factor, so we need to improve that part and it is expected to be a good simulator to measure the system's overall performance by exploiting SSD's internal architectures.

• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.29-37
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• 2024

In this paper, we propose an efficient image processing system to detect and track the movement of specific objects such as patients. The proposed system extracts the outline area of an object from a binarized difference image by applying a thinning algorithm that enables more precise detection compared to previous algorithms and is advantageous for mixed-mode design. The binarization and thinning steps, which require a lot of computation, are designed based on RTL (Register Transfer Level) and replaced with optimized hardware blocks through logic circuit synthesis. The designed binarization and thinning block was synthesized into a logic circuit using the standard 180n CMOS library and its operation was verified through simulation. To compare software-based performance, performance analysis of binary and thinning operations was also performed by applying sample images with 640 × 360 resolution in a 32-bit FPGA embedded system environment. As a result of verification, it was confirmed that the mixed-mode design can improve the processing speed by 93.8% in the binary and thinning stages compared to the previous software-only processing speed. The proposed mixed-mode system for object recognition is expected to be able to efficiently monitor patient movements even in an edge computing environment where artificial intelligence networks are not applied.

• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1754-1766
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• 1993

The application of VXIbus system, an Industry standard, is rapidly spreading with its ability to offer the easiness of integration from GPIB and the fast data transmission from VMEbus system. Compared with VXIbus Register Based Device, VXIbus Message Based Device has a drawback In the aspect of speed. But it is possible to utilize high level ASCII commands to control a Message Based Device, therefore system integration is much easier with Message Based Device than with Register Based Device. And, the FFT analyzer is an instrument for signal analysis which can be inexpensively implemented to be fast and have high resolution. Its wide ability of analysis presents numerous application. So, it is necessary to apply VXIbus system to FFT analyzer. In this paper, the implementation of FFT analyzer is performed using a DSP module and by implementing all A/D conversion circuit and a control module which performs VXIbus interface. The device can be controlled by Slot0 Commender which supports VXIbus Shared Memory Protocol through VXIbus.

• The Journal of Society for e-Business Studies
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• v.12 no.2
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• pp.195-217
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• 2007

B2B registries provide spaces to register and retrieve information which is necessary to support B2B transactions among business partners or potential business partners. Business process specifications are one of important contents in B2B registries, and there is high complexity of representation due to complex and dynamic characteristics of business processes. Also, currently there exist several competing specification frameworks such as ebXML BPSS, WSBPEL, BPMN, and so on. This paper proposes a metadata schema to register business process specifications which are represented by different specification frameworks. The proposed schema has extensibility to register business process specifications which are represented by various different specification frameworks. Also, it extends reuse level from whole business specification processes to their components. To show the usefulness of the proposed schema, this paper demonstrates metadata extraction from business process specifications which are represented by two representative XML-based business process specification languages, ebXML BPSS and WSBPEL.

• Journal of Environmental Health Sciences
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• v.48 no.5
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• pp.272-281
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• 2022

Background: The constant consumption of chemical products owing to expanding industrialization has led to an increase in public interest in chemical substances. As the production and disposal processes for these chemical products cause environmental problems, regional information on the hazard level of chemical substances is required considering their effects on humans and in order to ensure environmental safety. Objectives: This study aimed to identify hazard contribution and spatiotemporal characteristics by region and chemical by calculating a hazard-based result score using pollutant release and transfer register (PRTR) data. Methods: This study calculated the chemical discharge and hazard-based result score from the Risk-Screening Environmental Indicators (RSEI) model, analyzed their spatiotemporal patterns, and identified hotspot areas where chemical discharges and high hazard-based scores were concentrated. The amount of chemical discharge and hazard-based risk scores for 250 cities and counties across South Korea were calculated using PRTR data from 2011 to 2018. Results: The chemical discharge (high densities in Incheon, Daegu, and Busan) and hazard-based result scores (high densities in Incheon, Chungcheongnam-do, and some areas of Gyeongsangnam-do Province) showed varying spatial patterns. The chemical discharge (A, B) and hazard-based result score (C, D) hotspots were identified. Additionally, identification of the hazard-based result scores revealed differences in the type of chemicals contributing to the discharge. Ethylbenzene accounted for ≥80% of the discharged chemicals in the discharge hotspots, while chromium accounted for >90% of the discharged chemicals in the hazard-based result score hotspots. Conclusions: The RSEI hazard-based result score is a quantitative indicator that considers the degree of impact on human health as a toxicity-weighted value. It can be used for the management of industries discharging chemical substances as well as local environmental health management.