• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2009년 추계학술발표대회
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• pp.76-76
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• 2009

눈부신 전자산업의 발달로 대부분의 전자제품이 다기능/경박단소화 되고 있어, 고밀도 실장 기술인 양면 표면실장과 고집적 패키징 기술인 패키지 적층 공정의 적용이 점차 확대되고 있다. 따라서 양면 표면실장 및 패키지 적층 공정에 사용되는 저온 접합용 무연 솔더 즉, $183^{\circ}C$(Sn-37Pb 공정 솔더 융점) 이하의 융점을 가지는 저온 무연 솔더에 대한 관심이 높아지고 있다. 한편, 미세피치 적용 분야에 있어 ACF/P를 이용한 COG 접속 분야 외에도 최근 저온 접합용 무연 솔더를 이용한 접속 분야가 각광을 받고 있다. 따라서, 접속피치 미세화에 대응하기 위해 스크린 인쇄성을 향상시킬 수 있는 저온 무연 솔더 paste 제조 및 공정 기술의 개발이 필요한 실정이다. 현재 대표적인 저온 무연 솔더 조성은 Sn-Bi계($138^{\circ}C$ 융점)와 Sn-In계($120^{\circ}C$ 융점)이다. 하지만, 이들 조성의 신뢰성 등에 있어 개선의 여지가 있으므로 이를 해결하기 위한 무연솔더 조성의 개발이 필요하다. 이와 같은 관점에서, 본 연구는 $137^{\circ}C$의 융점을 갖는 Sn-57.6Ag-0.4Ag 저온 무연 솔더 paste를 $217^{\circ}C$의 융점을 갖는 Sn-3.0Ag-0.5Cu 솔더 paste와 비교하여 인쇄성, reflow 특성, void inspection, 미세조직 관찰 및 underfill 적용 등의 실험을 실시하였다.

• 한국자동차공학회논문집
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• 제21권1호
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• pp.145-153
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• 2013

In this study, shear punch-creep (SP-Creep) at Sn-4Ag/Cu pad the joint was tested by using environment-friendly Pb-free solder alloy Sn-4Ag of electronic components. Pb eutectic alloy (Sn-37Pb) joints limited to environmental issues with reflow time (10sec, 30sec, 100sec, 300sec) according to two types of solder alloy joints are compared and evaluated by creep strain rate, rupture time and IMC (Intermetallic Compound) behavior. As the results, reflow time increases with increasing thickness of IMC can be seen at overall 100sec later in case of two solder joints on the IMC thickness of Sn-4Ag solder joints thicker than Sn-37Pb solder joints. In addition, when considering creep evaluation factors, lead-free solder alloy Sn-4Ag has excellent creep resistance more than Pb eutectic alloy. For this reason, the two solder joints, such as in the IMC (Cu6Sn5) was formed. However, the creep resistance of Sn-4Ag solder joints was largely increased in the precipitation strengthening effect of dispersed Ag3Sn with interface more than Sn-37Pb solder joints.

• 청정기술
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• 제11권4호
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• pp.205-211
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• 2005

마이크로렌즈 어레이의 제작은 매우 다양한 재료와 방법이 제안되어 지고 있으나, 폴리머를 이용한 사출법은 광학적 특성, 내충격성, 가공성, 경량화 및 환경친화성 등의 장점으로 주목 받고 있다. 사출법 템플레이트를 제작하기 위한 PR(Photo-Resist) reflow법은 형상제어가 용이하고 대량생산과 정밀가공의 측면에서 효율적이어서, 집적화가 용이하고 공정을 줄일 수 있는 장점을 갖게 되어 매우 환경친화적이다. 그러나 마이크로렌즈 어레이의 사출성형은 사용되는 폴리머재료의 성질에 따라 성형에 어려움이 있는 것으로 알려져 있다. 본 연구에서는 이와 같은 성형의 어려움을 극복하기 위한 방법으로 급가열/급냉각 사출을 통하여 마이크로렌즈 어레이를 제작하고 특성을 이해하였다. 템플레이트의 급격한 온도상승과 고온에서의 모양이 냉각으로 인한 변형이 없도록 급속히 냉각시켜 줌으로서 마이크로렌즈 어레이의 사출성형을 구현 하였다. PC(Poly-Cabon ate)와 PMMA(Poly-Methyl-Meth-Acrylate)를 비교하여, PMMA가 낮은 용융점에 의해 성형성이 우수함을 확인하였다. 사출시 압력과 속도를 변수로 마이크로렌즈 어레이의 제작을 위한 사출조건을 도출하였다.

• 한국광학회지
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• 제16권4호
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• pp.340-344
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• 2005

화염가수분해 증착법(FHD : Flame Hydrolysis Deposition)으로 제작된 Ge이 첨가된 BPSG(Boro-Phospho-Silicate-Glass)막의 표면을 절단톱(dicing saw)을 이용하여 일정한 깊이로 절단함으로써 각 단위 마이크로렌즈 셀들을 형성시켰다. 또한 절단된 각 단위 마이크로렌즈 셀들을 가열용융(thermal reflow) 방법을 이용하여 $1200^{\circ}C$에서 가열용응시킴으로써 직경이 $53.4{\mu}m$인 마이크로렌즈 어레이를 제작할수 있었다. 이 때 렌즈간 간격은 $70{\mu}m,$ 렌즈 두께는 약 $28.4{\mu}m$이었다. 제작된 마이크로렌즈 어레이의 형상을 이미지-프로세스로 분석하였으며. 초점거리는 $62.2{\mu}m$이었다. 본 제작방법은 일반적인 사진식각 공정을 이용한 마이크로렌즈 제작보다 간단하면서도 저렴한 비용으로 제작이 가능하다. 또한 곡률반경의 조절이 용이하고, 보다 정밀하며 다양한 마이크로렌즈 어레이를 구현할 수 있다.

• 대한금속재료학회지
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• 제48권11호
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• pp.1041-1046
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• 2010

The reactions between a Sn-3.0Ag-0.5Cu solder alloy and electroless Ni/electroless Pd/immersion Au (ENEPIG) surface finishes with various Pd layer thicknesses (0, 0.05, 0.1, 0.2, $0.4{\mu}m$) were examined for the effect of the Pd layer on the massive spalling of the $(Cu,Ni)_6Sn_5$ layer during reflow at $235^{\circ}C$. The thin layer deposition of an electroless Pd (EP) between the electroless Ni ($7{\mu}m$) and immersion Au ($0.06{\mu}m$) plating on the Cu substrate significantly retarded the massive spalling of the $(Cu,Ni)_6Sn_5$ layer during reflow. Its retarding effect increased with an increasing EP layer thickness. When the EP layer was thin (${\leq}0.1{\mu}m$), the retardation of the massive spalling was attributed to a reduced growth rate of the $(Cu,Ni)_6Sn_5$ layer and thus to a lowered consumption rate of Cu in the bulk solder during reflow. However, when the EP layer was thick (${\geq}0.2{\mu}m$), the initially dissolved Pd atoms in the molten solder resettled as $(Pd,Ni)Sn_4$ precipitates near the solder/$(Cu,Ni)_6Sn_5$ interface with an increasing reflow time. Since the Pd resettlement requires a continuous Ni supply across the $(Cu,Ni)_6Sn_5$ layer from the Ni(P) substrate, it suppressed the formation of $(Ni,Cu)_3Sn_4$ at the $(Cu,Ni)_6Sn_5/Ni(P)$ interface and retarded the massive spalling of the $(Cu,Ni)_6Sn_5$ layer.

• 소성∙가공
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• 제17권5호
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• pp.322-327
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• 2008

LGP is a key component of LCD back light unit because it determines brightness and sharpness of the display image. Usually, it has optical patterns fabricated on the bottom surface. These optical patterns convert point or line sources placed in the side of LGP to plane source at the top surface by changing the propagating direction of the incident light. In the present paper the LiGA-reflow method was applied to fabricate the LGP mold. Furthermore, the optical simulation considering the replication ratio of pattern height was applied to the pattern design. The optical simulation through systematic correction scheme was adopted to find the optimum distribution of pattern density. Finally, the stamper fabricated by this method was installed in the mold and LGP was produced by injection molding. As a result of luminance measurement for the final product, the average luminance and luminance uniformity was measured 3,180 nit and 84%, respectively. Consequently, the mold fabrication method using the LiGA-reflow and optical simulation(CAE) can save the expense and time compared with the existing fabrication methods(laser ablation and chemical etching).

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.351-357
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• 2005

솔더/UBM 계면반응에 따른 솔더범프의 기계적 신뢰성을 평가하기 위한 방안으로서 Cu UBM 상에서 리플로우한 Sn-52In 솔더범프의 리플로우 조건에 따른 전단응력과 전단에너지의 변화거동을 비교하였다. 리플로우 조건에 따른 전단에너지의 변화거동이 전단강도에 비해 Sn-52In/Cu 계면반응 및 파괴모드의 변화거동과 훨씬 잘 일치하여 솔더/UBM 계면반응에 따른 기계적 신뢰성을 분석하는데 전단에너지가 전단강도보다 훨씬 효과적인 평가 방안임을 알 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of Welding and Joining
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• 제19권3호
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• pp.305-310
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• 2001

UBM-coated Si-wafer was fluxlessly soldered with glass substrate in $N_2$ atmosphere using plasma cleaning method. The bulk Sn-37wt.%Pb solder was rolled to the sheet of $100\mu\textrm{m}$ thickness in order to bond a solder disk by fluxless 1st reflow process. The oxide layer on the solder surface was analysed by AES(Auger Electron Spectroscopy). Through rolling, the oxide layer on the solder surface became thin, and it was possible to bond a solder disk on the Si-wafer with fluxless process in $N_2$ gas. The Si-wafer with a solder disk was plasma-cleaned in order to remove oxide layer formed during 1st reflow and soldered to glass by 2nd reflow process without flux in $N_2$ atmosphere. The thickness of oxide layer decreased with increasing plasma power and cleaning time. The optimum plasma cleaning condition for soldering was 500W 12min. The joint was sound and the thicknesses of intermetallic compounds were less than $1\mu\textrm{m}$.