• Proceedings of the KIPE Conference
• /
• 2004.07b
• /
• pp.575-578
• /
• 2004

The performance of an active power filter(APF) depends on the inverter characteristic, the control method, and the accuracy of reference signal generator. The accuracy of reference generator is the most critical item to determine the performance of active power filter. This paper introduces a novel reference signal generator composed of improved adaptive predictive filter. The performance of proposed reference signal generator was first verified through a simulation with MATLAB. Furthermore, the application of feasibility was evaluated through experimenting with a single-phase APF prototype based on the proposed reference generator, which was implemented using the TMS320C31 floating-point signal processor. Both simulations and experimental results confirm that our reference signal generator can be used successfully in practical active power filters.

• Proceedings of the KIEE Conference
• /
• 2003.04a
• /
• pp.212-216
• /
• 2003

The performance of active power filter depends on the inverter characteristic, the control method, and the accuracy of reference signal generator. The accuracy of reference generator is the most critical item to determine the performance of active power filter. This paper introduces a novel reference signal generator composed of improved adaptive predictive filter. The performance of proposed reference signal generator was verified by means of simulation with MATLAB. The simulation result confirm that the proposed reference signal generator can be utilized for the active power filter.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.6
• /
• pp.592-601
• /
• 2004

The performance of active power filter depends on the inverter characteristic, the control method, and the accuracy of reference signal generator. The accuracy of reference signal generator is the most critical item to determine the performance of active power filter. This paper introduces a novel reference signal generator composed of improved adaptive predictive filter. The performance of proposed reference signal generator was verified by means of simulation with MATLAB. The application feasibility was evaluated by building and experimenting a single-phase active power filter based on the proposed reference generator, which was implemented in the DSP(digital signal processor) TMS320C31. Both simulation and experimental results confirm that the proposed reference signal generator can be utilized for the active power filter.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.2
• /
• pp.106-111
• /
• 2015

Since most reference voltage generator circuits have bi-stable characteristics, it is important to employ a proper start-up circuit to operate a reference generator in the desired state. In this paper, we propose a start-up circuit for a low voltage reference generator. This start-up circuit determines the state of the circuit reliably by measuring the current drawn by BJTs in the circuit, which is well-defined in the desired state. To measure the current using CMOS-compatible devices only, a comparator with an internal offset voltage is used. The reliability of the proposed circuit is confirmed by Monte-Carlo simulations of the start-up operation, which show that, with the proposed start-up circuit, the low voltage reference generator starts reliably with supply voltages over 850mV even in the presence of device mismatches.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.10a
• /
• pp.785-788
• /
• 2007

The newly proposed badgap reference voltage generator is insensible to PVT(process, voltage, temperature) variation and has a lower minimum supply voltage, which is required for stable operation. The simulation result is that the bandgap reference voltage generator starts operation at 1.0V of supply voltage. The layout of the bandgap reference voltage generator is designed using Magnachip $0.18{\mu}m$ DDI process, and the size is $409.36{\mu}m$ ${\times}$ $435.46{\mu}m$.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.8 no.5
• /
• pp.435-441
• /
• 2003

Dynamic Voltage Restorers (DVR)s are known as the best effective and economic means to compensate for voltage sags and swells. This paper proposes a novel method to generate reference voltages synchronized with the grid whether the line voltages are distorted by a fault or not. The proposed reference wave generator (RWG) looks for the original wave forms from the corrupted line voltages and synthesizes the expected positive sequence reference waves for DVRs. There is no transient problem on the generated reference waves when the line voltages are distorted by the fault.

• Journal of electromagnetic engineering and science
• /
• v.9 no.3
• /
• pp.118-123
• /
• 2009

This paper discusses the design and fabrication of a reference signal generator for a naval radar system, including the vibration environment test. The transmit signals of the S-band radar system are synthesized by the reference signal and the phase noise must lower than - 130 dBc/Hz at a 10 kHz offset frequency. To achieve this specification, the phase noise of the reference signal needs to be less than -165 dBc/Hz at a 10 kHz offset. For achieving very low phase noise performance by the reference signal generator, the phase locked loop technique is applied with a 10 Hz loop bandwidth. Also, this reference signal generator has ${\pm}0.35\;ppb$ short-term stability to minimize instant phase errors and high vibration sensitivity against a ship's shaking, unbalanced rotating of antennas and so on.

• Journal of Power Electronics
• /
• v.8 no.4
• /
• pp.345-353
• /
• 2008

In this paper, a novel loss minimization of an induction generator in wind energy generation systems is presented. The proposed algorithm is based on the flux level reduction, for which the generator d-axis current reference is estimated using support vector regression (SVR). Wind speed is employed as an input of the SVR and the samples of the generator d-axis current reference are used as output to train the SVR algorithm off-line. Data samples for wind speed and d-axis current are collected for the training process, which plots a relation of input and output. The predicted off-line function and the instantaneous wind speed are then used to determine the d-axis current reference. It is shown that the effect of loss minimization is more significant at low wind speed and the loss reduction is about to 40% at 4[m/s] wind speed. The validity of the proposed scheme has been verified by experimental results.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.2
• /
• pp.451-454
• /
• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• 한국정보통신설비학회:학술대회논문집
• /
• 2005.08a
• /
• pp.159-165
• /
• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.