• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Korean Society of Safety
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• v.35 no.1
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• pp.1-11
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• 2020

Article 325 (Prevention of Fire Explosion due to Electrostatic) of the Rule for Occupational Safety and Health Standard specifies that in order to prevent the risk of disasters caused by static electricity, fire, explosion and static electricity in the production process, However, in order to do this, it is absolutely necessary to use a pre-detection technology and a detector for antistatic discharge prediction, which is a precautionary measure by static electricity in a fire / explosion hazard place, but in Korea, And there is no technical standard for the application of the technology of the explosion proof structure of the related equipment. Research methods include domestic and overseas electrostatic discharge detection technology and literature investigation of related equipment explosion proofing technology, domestic and foreign electrostatic discharge detection device production and use situation investigation, advanced foreign technology data analysis and benchmarking. In particular, we sought to verify the results of empirical experiments using electrostatic discharge detection technology through sample purchase and analysis of related major products, development of optimization technology through prototype production, evaluation, and supplementation, and expert knowledge through expert consultation. The results of this study were developed and fabricated two prototypes of electrostatic discharge detector based on the technology / standard related to electrostatic discharge detection technology in Korea and abroad through development of electrostatic discharge detection technology and development and production of detector. In addition, based on the development of electrostatic discharge detection technology, we developed an intrinsic safety explosion proof ib class explosion proof technology applicable to the process of using and handling flammable gas and flammable liquid vapor and combustible dust. In the case of the over voltage and minimum voltage are supplied to the explosion-proof structure ESD detector, check the state of the circuit and the transient and transient currents generated by the coil and capacitor elements during the input and standby of the signal pulse voltage. Explosion-proof equipment-Part 11: Intrinsically safe explosion proof structure The comparative evaluation with the reference curve in Annex A of "i" confirms that the characteristics of the intrinsically safe explosion protection structure are met.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.3
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• pp.38-46
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• 2012

Atrial fibrillation is needed to be detected at paroxysmal stage and to be treated. But, paroxysmal atrial fibrillation ECG is hardly obtained with 12-lead electrocardiographs but Holter systems. Presently, the averaged beat subtraction(ABS) method is solely used to estimate atrial fibrillatory waves even with somewhat large residual error. As an alternative, in this study, we suggested an ESAF(event-synchronous adaptive filter) based algorithm, in which the AF ECG was treated as a primary input and event-synchronous impulse train(ESIT) as a reference. And, ESIT was generated so to be synchronized with the ventricular activity by detecting QRS complex. We tested proposed algorithm with simulated AF ECGs and real AF ECGs. As results, even with low computational cost, this ESAF based algorithm showed better performance than the ABS method and comparable performance to algorithm based on PCA(principal component analysis) or SVD(singular value decomposition). We also proposed an expanded version of ESAF for some AF ECGs with multi-morphologic ventricular activities and this also showed reasonable performance. Ultimately, with Holter systems including our proposed algorithm, atrial activity signal can be precisely estimated in real-time so that it will be possible to calculate atrial fibrillatory rate and to evaluate the effect of anti-arrhythmic drugs.

• Korean Journal of Optics and Photonics
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• v.15 no.4
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• pp.299-308
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• 2004

We proposed more efficient encoding methods that can design a multi-channel multi-level phase only computer-generated hologram(CGH) that can reconstruct many objects simultaneously without a conjugate image. We used a fabrication technique for the pixel oriented CGH for designing the pattern of the proposed multi-channel CGH. We investigated the difference of the optical efficiency(η), mean square error(MSE) and signal-to-noise ratio(SNR) of multi-channel CGHs that were designed by three kinds of encoding methods according to the number of quantization phase levels, and we estimated the performance of the pattern of the proposed multi-channel CGH. Generally, as the number of input objects' reference patterns stored in the CGH is increased, the reconstruction quality of the CGH is degraded. But we observed through computer simulation that the diffraction efficiency of the 1-ch CGH is 70%, and those of the 2-ch, 4-ch, 8-ch CGHs are 62%, 62% and 63%. Therefore we found that the diffraction efficiencies of the multi-channel CGHs using the newly proposed encoding method are similar to that of 1-ch CGH. We implemented the CGH optically using a liquid crystal spatial light phase modulator that consisted of a PAL-SLM efficiently coupled with a XGA type LCD by an optical lens and an LD for illuminating the LCD. We discussed the output images that are reconstructed from the PAL-SLM.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.51-56
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• 2000

Is this paper, we studied on the automatic speech control system in real-time windows environment using voice recognition. The applied reference pattern is the variable DMS model which is proposed to fasten execution speed and the one-stage DP algorithm using this model is used for recognition algorithm. The recognition vocabulary set is composed of control command words which are frequently used in windows environment. In this paper, an automatic speech period detection algorithm which is for on-line voice processing in windows environment is implemented. The variable DMS model which applies variable number of section in consideration of duration of the input signal is proposed. Sometimes, unnecessary recognition target word are generated. therefore model is reconstructed in on-line to handle this efficiently. The Perceptual Linear Predictive analysis method which generate feature vector from extracted feature of voice is applied. According to the experiment result, but recognition speech is fastened in the proposed model because of small loud of calculation. The multi-speaker-independent recognition rate and the multi-speaker-dependent recognition rate is 99.08% and 99.39% respectively. In the noisy environment the recognition rate is 96.25%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.