• Proceedings of the KIEE Conference
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• 2000.11a
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• pp.139-141
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• 2000

High voltage direct current(HVDC) transmission system uses the phase controlled rectifier triggered by means of IPC(individual phase control) or EPC(equidistant pulse control). Most HVDC system has adopted EPC method that can solve the harmonic instability problem of IPC method in weak power system. But EPC has inherent indirect synchronizing problem requiring the closed loop control. This paper presents the new gate pulse generating method for 12-pulse HVDC converter, which combines IPC with EPC. Simulation and test results are presented. The basic concept is that it generates the gating pulse for 12-pulse converter by synthesizing the internal phase reference using the frequency and phase information of a sin91e phase voltage. To ensure the reliability of the external phase input, Potential transformer that detects the phase voltage has redundancy. Using fault detecting algorithm the healthy input is always guaranteed. And the frequency compensation function was reinforced.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.6
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• pp.473-480
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• 2016

This study proposes a performance improvement for parallel-connected thyristor dual converters using a circulating current with an unbalanced parallel operation compensator. The proposed control method determines a variable reference value for the voltage PI controller according to voltage error at firing angle control applied to a difference current control. This method uses circulating current control to maintain a stable voltage and excellent current response during parallel operation. The effectiveness of the proposed control is verified with a simulation and an experiment based on the comparison of the performance of the proposed control method with other conventional methods.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.1-10
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• 2015

This paper proposes a control algorithm for permanent magnet synchronous generators with a back-to-back three-level neutral-point clamped voltage source converter in a medium-voltage off-shore wind power system under unbalanced grid conditions. Specifically, the proposed control algorithm compensates for unbalanced grid voltage at the PCC (Point of Common Coupling) in a collector bus of an off-shore wind power system. This control algorithm has been formulated based on symmetrical components in positive and negative synchronous rotating reference frames under generalized unbalanced operating conditions. Instantaneous active and reactive power is described in terms of symmetrical components of measured grid input voltages and currents. Negative sequential component of AC input current is injected into the PCC in the proposed control strategy. The amplitude of negative sequential component is calculated to minimize the negative sequential component of grid voltage under the limitation of current capability in a voltage source converter. The proposed control algorithm enables the provision of balanced voltage at the PCC resulting in the high quality generated power from off-shore wind power systems under unbalanced network conditions.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.215-216
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• 2014

This paper proposes a control algorithm for permanent magnet synchronous generator with a back-to-back three-level neutral-point clamped voltage source converter in a medium-voltage offshore wind power system under unbalanced grid conditions. The proposed control algorithm particularly compensates for the unbalanced grid voltage at the point of common coupling in a collector bus of offshore wind power system. This control algorithm has been formulated based on the symmetrical components in positive and negative rotating synchronous reference frames under generalized unbalanced operating conditions. Instantaneous active and reactive power are described in terms of symmetrical components of measured grid input voltages and currents. Negative sequential component of ac input current is injected to the point of common coupling in the proposed control strategy. The amplitude of negative sequential component is calculated to minimize the negative sequential component of grid voltage under the limitation of current capability in a voltage source converter. The proposed control algorithm makes it possible to provide a balanced voltage at the point of common coupling resulting in the generated power of high quality from offshore wind power system under unbalanced network conditions.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.11
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• pp.563-571
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• 2003

In this paper, the control algorithm and control method for a combined system of shunt passive filter and series active filter in 3-phase 4-wire system are discussed. Moreover, the three-phase four-wire system is widely employed in distributing electric energy to several office building and manufacturing plants. In such systems, the third harmonic and its 3th harmonics are termed as triple and zero sequence components that do not cancel each other in the system neutral. Consequently, the triple harmonics add together creating a primary source of excessive neutral current. Regarding this concern, this paper presents a new control algorithm for a series hybrid active system, whereas the control approach it adopts may directly influence its compensation characteristics. Hence, the advantage of this control algorithm is direct extraction of compensation voltage reference and the required rating of the series active filter is much smaller than that of a conventional shunt active filter. Some experiments were executed and experimental results from a prototype active power filter confirm the suitability of the proposed approach.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.48-58
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• 1998

For the purpose of designing novel capacitance pressure sensor, several effects on sensitivity such as parasitic capacitance effects, temperature/thermal drift and leakage current have to be eleiminated. This paper proposed the experimental studies on frequency compensation method by electronic circuit technique, C-V converting method with switched capacitor and C-F converting method with schmitt trigger circuit. The third interface circuit by frequency compensation method is composed to eliminate the drift and leakage component by comparision sensing frequency with reference frequency. The signal transmission is realized by digital signal to minimize the influence of noise and high resolution is obtained by means of increasing the number of digital bits. In the fabricated high performance C-V interface, the offset voltage was not appeared, and in case of voltage source, 4.0V, feed back capacitance, 10㎊, the pressure, 0~10 ㎪, the sensitivity of C-V converter is 28 ㎷/㎪.V, the temperature drift characteristic, 0.051 %F.S./$^{\circ}C$ and C-F converter shows -6.6 Hz/pa, 0.078 %F.S./$^{\circ}C$ respectively, relatively good ones.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.2
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• pp.82-87
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• 2017

This paper presents performance improvement of CO gas sensor signal conditioner for early fire warning system. The warning system is based on the CO sensor and its advanced signal conditioning modules network that employ electochemical gas sensor. The electochemical has advantage of having a linear output and operating with a low consumption and fast response. This electrochemical gas sensor contains a gas membrane and three electrodes(working, counter, reference electrode) in contact with an electrolyte. To use a three-electrode sensor, a voltage has to be applied between the working and the reference electrode according to the specification of the sensor. In this paper, we designed these requirements that should be considered in temperature compensation algorithm and electrode measurement of CO sensor modules by using advanced signal conditioning method included 3-electrode. Simulation and experimental results show that signal conditioner of CO sensor module using 3-electrode have a advantage linearity, sensitivity and stability, fast response etc..

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.7
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• pp.500-508
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• 2000

Basic design for single-phase active power filter, which aims at railway application provided with PWM-controlled converters, is comprehensively studied and its performance is presented in this paper. Active power filters are used to compensate railway signaling and public telecommunication interference due to the high-order harmonic currents generated in railway traction locomotives. A type of hybrid digital filter which is composed of low pass filter and high pass filter is proposed so that the desired harmonic reference current with accurate magnitude and phase shift can be extracted from catenary line current. A design criteria to determine input inductor L and output capacitor C is also described, considering voltage, current, PWM pattern, and switching frequency of the main converters. Finally, computer simulation and DSP-based experiments resulted from laboratory test are presented.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.173-179
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• 2001

This paper represents the control algorithm of the instantaneous voltage sag corrector for the power quality enhancement in distribution line. Especially, a novel detection technique of the symmetrical components is proposed for the analysis of the three-phase unbalanced and asymmetrical problems caused by the single line ground fault which is he most frequent event. This proposed method is based on the simple calculation and the control references of the symmetrical components for voltage compensation can be described as dc value without any other phase detection procedure. And also, for the generation of the reference voltages, the UF and MF defined by IEC is considered. Using this proposed control algorithm, the compensator has the fast dynamic characteristics and the THD of the compensated voltage waveform is very low. Finally, the validity of the proposed algorithm is proved by the PSCAD/EMTDC simulation and experimental results.