• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1238-1244
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• 1999

In this paper, a new design of a triple-erroe-correcting (TEC) Reed-Solomon decoder is presented based on direct decoding method which is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 GF(2m) multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders needs 24 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of implementation. Futhermore, the proposed TEC Reed-Solomon decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Review of KIISC
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• v.2 no.3
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• pp.42-57
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• 1992

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.4
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• pp.427-438
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• 1998

The bit error rate(BER) performance of Trellis Coded QPSK signal in the presence of cochannel interference (CCI) and Rician fading is investigated. The trellis coded QPSK system adopts Maximum Ratio Combining (MRC) diversity reception and Reed-Solomon code to enhance system performance. Using the derived error probability equation, the error performance of trellis coded QPSK system has been evaluated and shown in figures to discuss as a function of signal power to noise power ratio (SNR), signal power to interference power ratio(SIR), direct to indirect signal power ratio ($K_R$), the number of diversity branch (M), the frame length of Reed-Solomon code (n), the number of error correction symbol (t), and the number of state of trellis encoder. From the results, we know that proposed system is affected by cochannel interference and fading in microcell environment. Also, BER performance of Trellis Coded QPSK system can be improved as increasing either the power of desired signal or the value of SIR. And the BER floor in microcellular system is caused by the cochannel interference and it occurs at high BER when SIR is low. And Reed-Solomon code (n=15, t=2) is more effective to restrain the affection of CCI and fading than MRC diversity reception (M=2).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.191-196
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• 2011

In this paper, we propose a design method of Reed-Solomon (23, 17) decoder for UWB using direct decoding method. The direct decoding algorithm is more efficient for the case of relatively small error correction capability. The proposed decoder requires only 9 $GF(2^m)$ multipliers in obtaining the error-locator polynomial and the error-evaluator polynomial, whereas other decoders need about 20 multipliers. Thus, the attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• Journal of applied mathematics & informatics
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• v.31 no.5_6
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• pp.785-794
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• 2013

Soon after Lee and O'Sullivan proposed a new interpolation algorithm for algebraic soft-decision decoding of Reed-Solomon codes, there have been some attempts to apply a coordinate transformation technique to the new algorithm, with a remarkable complexity reducing effect. In this paper, a conceptually simple way of applying the transformation technique to the interpolation algorithm is proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1C
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• pp.8-13
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• 2006

A new RS(Reed Solomon) Decoder design method, using Galois Subfield GF($2^4$) Multiplier, is described. The Decoder is designed using Normalized error position stored ROM. Here New Inverse Calculator in GF($2^8$) is designed, which is simpler and faster than the classical GF($2^8$) direct inverse calculator, using the Galois Subfield GF($2^4$) Arithmatic operator.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.19-26
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• 1993

The bit error probability of Reed-Solomon/convolutional concatenated codes can be more exactly calculated by using a more approximate bound of the symbol error probability of the convolutional codes. This paper obtains the unequal symbol error bound of the convolutional codes, and applies to the calculation of the bit error probability of the concatenated codes. Our results are tighter than the earlier studied other bounds.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.938-941
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• 1999

In this paper, we designed a pipeline (15,9) Reed-solomon decoder. To compute the error locator polynomials, we used the Euclidean algorithm. This algorithm includes computation of inverse element. We avoided the inverse element calculation in this RS decoder by using ROMs. We designed this decoder using VHDL. Simulation results show that the designed decoder corrects three error symbols. We implemented this design through an Altera FPGA chip.