• The Journal of the Korea Contents Association
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• v.6 no.2
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• pp.162-168
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• 2006

This paper presents a high performance CORDIC circuit based on redundant numbers yielding a minimal number of iteration stages. The minimal number of iteration stages reflects the iteration number yielding a smaller computation error than the truncation error. The minimal number of iterations is found n-4 for $n\geq16$, where n is the number of input angle bits. The CORDIC circuit is based on a redundant number system with a constant scale factor The circuit performs sine and cosine calculations with a delay of {5 (n-4)+ 2[$log_{2}n$]}$\DeltaT$.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.68-75
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• 1992

In this paper the back-propagation algorithm through omitting redundant learning has been proposed to improve learning speed. The proposed algorithm has been applied to XOR, Parity check and pattern recognition of hand-written numbers. The decrease of the number of patterns to be learned has been confirmed as learning proceeds even in early learning stage. The learning speed in pattern recognition of hand-written numbers is improved more than 2 times in various cases of hidden neuron numbers. It is observed that the improvement of learning speed becomes better as the number of patterns and the number of hidden numbers increase. The recognition rate of the proposed algorithm is nearly the same as that conventional method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.11
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• pp.491-494
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• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.122-128
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• 2003

In this paper, a 16${\times}$16-bit Multiplier and Accumulator (MAC) is designed using a Redundant Binary Adder (RBA) circuit so that it can make a fast addition of the Redundant Binary Partial Products (RB_PP's) by using Wallace-tree structure. Because a RBA adds two RB numbers, it acts as a 4-2 compressor, which reduces four inputs to two output signals. We propose a method to convert the Redundant Binary (RB) representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient RB number to binary number converter can be designed with new conversion method.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.365-368
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• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Steel and Composite Structures
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• v.49 no.2
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• pp.125-141
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• 2023

Firstly, a new kind of prismatic tensegrity structures with redundant cables is defined, the topology, geometry and forming conditions of which are introduced further. The development of its mechanical properties including self-stress states and structural stiffness with the increment of the twist angle is also investigated carefully. Combined with the topology of this kind of structures, a reasonable erection scheme is proposed, in which some temporary lifting points need to be set and two groups of vertical cables are tensioned in batches. Then, a simplified dynamic relaxation method is employed to track the erection process inversely, which aims to predict each intermediate equilibrium state during the construction, and give the key structural parameters that can effectively guide the construction. The removal of the active cables, the relaxation or tension of the passive cables are simulated by controlling their axial stiffness, so that the structural composition as well as the serial numbers of the elements always keep invariant regardless of the withdrawal of the slack cables. The whole analysis process is clear in concept, simple to implement and easy to popularize. Finally, several examples are given to verify the practicability and effectiveness of the proposed method further.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1001-1004
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• 1993

The Multisensor Fusion Problem (MFP) deals with the methodologies involved in effectively combining together homogeneous or non-homegeneous information obtained from multiple redundant or disparate sensors in order to perform a task more accurately, efficiently, and reliably. The inherent uncertainties in the sensory information are represented using Fuzzy Numbers, -numbers, and the Uncertainty-Reductive Fusion Technique (URFT) is introduced to combine the multiple sensory information into one consensus -number. The MFP is formulated from the Information Theory perspective where sensors are viewed as information sources with a fixed output alphabet and systems are modeled as a network of information processing and processing and propagating channels. The performance of the URFT is compared with other fusion techniques in solving the 3-Sensor Problem.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.109-119
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• 1996

We propsoed a multiplexed optical correlation filter method for an optical parallel addition based on symbolic substitution. In the proposed mthod, we used redundant binary number which was easy to minimize the number of the symbolic substitution rules. We chose MACE filter which had very low sidelobes and good correlation peak compared with SDF filter as the optical correlation recognition filter and encoded input numbers properly to increase the discrimination capability. In order to minimize the number of symbolic substitution rules, sixteen input patterns were divided into six groups of the same addition results and six filters for recognizing the input patterns were used. these filters were multiplexed in two MMACE filter planes and the corresponding substitution method was proposed. Through the computer simulation, we confirmed the proposed method was suitable to implement the optical parallel adder.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.269-280
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• 1996

We proposed a symbolic substitution method based on an optical correlator for an optical parallel addition. In the proposed symbolic substitution method, we used redundant binary number of the symbolic substitution rules as a number system and chose MAC3E filter which had very low sidelobes and good correlation peak compared with SDF filter as the optical correlation filter. We encoeded input numbers property to increase the discrimination capability and divided inpt patterns into 5 groups of the same addition results to minimize the number of symbolic substitution rules. Through the computer simulation, we confirmed the proposed method was suitable to implement the optical parallel adder.