• Journal of Distribution Science
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• v.14 no.12
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• pp.61-69
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• 2016

Purpose - This study investigates the determinants that affect the number of IT Incident tickets of an IT Service Provider ("ITSP") to logistics industry in order to improve its management process by reducing the incident tickets. Research design, data, and Methodology - This study uses weekly data of IT incident tickets from September 2012 to June 2015. Correlation and regression analyses are conducted. Six identified determinants i.e., IT Change, User Errors, Shipment Volume, Network, Hardware and Software Issues are used as the explanatory variables. Results - Our findings show as following. First, our analysis indicates that IT Change is not a significant determinant as opposed to what commonly believed by many as the most important factor. Second, Software issue is the highest contributor to the Major IT incident tickets, followed by User Error, Network and Hardware issues. Third, it seems there is lead-lag relationship between IT Change and Major IT Incidents tickets as indicated by earlier studies. Fourth, the relationship between IT Change and Major IT tickets is also affected by shipment volume. Conclusions - As policy recommendation, all identified determinants should be treated according to priority. In addition, improving the way IT Changes are implemented will definitely reduce the IT incident tickets.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.365-370
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• 2016

The study about VR (Virtual Reality) has been done from the 1960s, but technical limits and high cost made VR hard to commercialize. However, in recent, high resolution display, computing power and 3D sensing have developed and hardware has become affordable. Therefore, normal users can get high quality of immersion and interaction. However, HMD devices which offer VR environment have high latency, so it disrupts the VR environment. People are usually sensitive to relative latency over 20ms. In this paper, as adding the Electromyogram (EMG) sensors to typical IMU sensor only system, the latency reduction method is proposed. By changing software and hardware components, some cases the latency was reduced significantly. Hence, this study covers the possibility and the experimental verification about EMG sensors for reducing the latency.

• Design & Manufacturing
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• v.12 no.1
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• pp.18-25
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• 2018

Both injection and injection molding dies have evolved into advanced technology. Product quality is also evolving day after day. Therefore, the conditions of the injection mold and the injection conditions are becoming important. In order to improve the quality of the product, the Hardware part of the mold has developed as an advanced technology, and the Software part has also developed with advanced technology. This study deals with the cooling part, which is part of the hardware. In addition to fluid cooling, which is commonly used in the industry, by using gas cooling identify the phenomena that appear on the surface of the product and the critical point strain of the product to find the optimal cooling. Electronic parts and automobile parts whose surface condition is important, the cooling process is important to such a degree that they are divided with good products and defective products according to the cooling process at the time of injection. By controlling this important cooling and reducing the injection time with additional cooling, the product quality can be increased to the highest production efficiency. In addition, high efficiency can be achieved without additional investment costs. This study was conducted to apply these various advantages in the field.

• Transactions of The Korea Fluid Power Systems Society
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• v.5 no.4
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• pp.1-9
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• 2008

In this paper, an energy regeneration algorithm is proposed to make the maximum use of the regenerative braking energy for a parallel hybrid electric vehicle(HEV) equipped with a continuous variable transmission(CVT). The regenerative algorithm is developed by considering the battery state of charge(SOC), vehicle velocity and motor capacity. The hydraulic module consists of a reducing valve and a power unit to supply the front wheel brake pressure according to the control algorithm. In order to evaluate the performance of the regenerative braking algorithm and the hydraulic module, a hardware-in-the-loop simulation (HILS) is performed. In the HILS system, the brake system consists of four wheel brakes and the hydraulic module. Dynamic characteristics of the HEV are simulated using an HEV simulator. In the HEV simulator, each element of the HEV powertrain such as internal combustion engine, motor, battery and CVT is modelled using MATLAB/$Simulink^{(R)}$. In the HILS, a driver operates the brake pedal with his or her foot while the vehicle speed is displayed on the monitor in real time. It is found from the HILS that the regenerative braking algorithm and the hydraulic module suggested in this paper provide a satisfactory braking performance in tracking the driving schedule and maintaining the battery state of charge.

• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• The Journal of Korea Robotics Society
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• v.17 no.3
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• pp.373-380
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• 2022

This paper considers a method of fast correspondence matching for iterative closest point (ICP) algorithm. In robotics, the ICP algorithm and its variants have been widely used for pose estimation by finding the translation and rotation that best align two point clouds. In computational perspectives, the main difficulty is to find the correspondence point on the reference point cloud to each observed point. Jump-table-based correspondence matching is one of the methods for reducing computation time. This paper proposes a method that corrects errors in an existing jump-table-based correspondence matching algorithm. The criterion activating the use of jump-table is modified so that the correspondence matching can be applied to the situations, such as point-cloud registration problems with highly curved surfaces, for which the existing correspondence-matching method is non-applicable. For demonstration, both hardware and simulation experiments are performed. In a hardware experiment using Hokuyo-10LX LiDAR sensor, our new algorithm shows 100% correspondence matching accuracy and 88% decrease in computation time. Using the F1TENTH simulator, the proposed algorithm is tested for an autonomous driving scenario with 2D range-bearing point cloud data and also shows 100% correspondence matching accuracy.

• Electronics and Telecommunications Trends
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• v.38 no.5
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• pp.34-50
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• 2023

Quantum error correction is a key technology for achieving fault-tolerant quantum computation. Finding the best decoding solution to a single error syndrome pattern counteracting multiple errors is an NP-hard problem. Consequently, error decoding is one of the most expensive processes to protect the information in a logical qubit. Recent research on quantum error decoding has been focused on developing conventional and neural-network-based decoding algorithms to satisfy accuracy, speed, and scalability requirements. Although conventional decoding methods have notably improved accuracy in short codes, they face many challenges regarding speed and scalability in long codes. To overcome such problems, machine learning has been extensively applied to neural-network-based error decoding with meaningful results. Nevertheless, when using neural-network-based decoders alone, the learning cost grows exponentially with the code size. To prevent this problem, hierarchical error decoding has been devised by combining conventional and neural-network-based decoders. In addition, research on quantum error decoding is aimed at reducing the spacetime decoding cost and solving the backlog problem caused by decoding delays when using hardware-implemented decoders in cryogenic environments. We review the latest research trends in decoders for quantum error correction with high accuracy, neural-network-based quantum error decoders with high speed and scalability, and hardware-based quantum error decoders implemented in real qubit operating environments.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.713-720
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• 2012

Recently, holography has received much attention as the next generation visual technology. Hologram is obtained by the optical capturing, but in recent years it is mainly produced by the method using computer. This method is named by computer generated hologram (CGH). Since CGH requires huge computational amount, if it is implemented by S/W it can't work in real time. Therefore it should use FPGA or GPU for real time operation. If it is implemented in the type of H/W, it can't obtain the same quality as S/W due to the bit limitation of the internal system. In this paper, we analyze the bit width for minimizing the degradation of the hologram and reducing more hardware resources and propose guidelines for H/W implementation of CGH. To do this, we performs fixed-points simulations according to main internal variables and arithmetics, analyze the numerical and visual results, and present the optimal bit width according to application fields.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.