• International Journal of Fuzzy Logic and Intelligent Systems
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• v.3 no.1
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• pp.105-111
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• 2003

This paper is researching the storing of 40 different kinds of conditions. Such as, car speed, delay in starting time and the volume of cars in traffic. Through the use of a central nervous networking system or AI, using 10 different intersecting roads. We will improve the green traffic light. And allow more cars to easily flow through the intersections. Now days, with increasing many vehicles on restricted roads, the conventional traffic light creates prove startup-delay time and end-lag-time. The conventional traffic light loses the function of optimal cycle. And so, 30-45% of conventional traffic cycle is not matched to the present traffic cycle. In this paper proposes electro sensitive traffic light using fuzzy look up table method which will reduce the average vehicle waiting time and improve average vehicle speed. Computer simulation results prove that reducing the average vehicle waiting time which proposed considering passing vehicle length for optimal traffic cycle is better than fixed signal method which dosen't consider vehicle length.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.893-894
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• 2006

DSP based on a 8 bit microprocessor was studied for ECG and PPG signals. Digital filtering has an advantage of reducing hardware components in system-on-chip design. However, low resolution such as in 8 bit data has much difficulties in DSP. We demonstrated a comparable performance of DSP filtering compared with analog filters.

• Korean Journal of Computational Design and Engineering
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• v.14 no.3
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• pp.168-175
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• 2009

A recent advance in RFID technology is one of the major technological drives in reducing cost in logistics, distribution and even in the manufacturing sector. However, currently the technology is practically accepted only in the area of logistics and inventory control. The characteristic of these application areas is that the technology is used in the controllable environment. In this paper, we discuss a case study of using active and passive RFID technologies to automatically gather process information in the mold factory. Active RFID tags are attached on the main parts of molds and their positions in the floor are tracked with the routers. We also discuss on the idea of using mobile device with RFID reader to inquire information for molds on the spot in the factory floor. The inquirable information includes 3D design data and basic mold data. The paper shows implementation results with hardware configuration for the testbed.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.11-16
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• 1993

VLIW architecture capable of testing multiple conditions in a cycle must support an efficient mechanism for multi-way branches. This paper proposes a mechanism to speed up the execution of multi-way branches and an efficient memory packing method of instructions, which reduced the wasted memory space. Also, we develops a new compiler technique which can transform program segments that are not applied to multi-way branches into ones that are applied to multi-way branches. The benefits gained by the transformation are to reduce branch penalty and to increase instruction-level parallelism.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.2
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• pp.142-147
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• 2007

In this paper we suggest a key distribution protocol based on ECC. This could be apply to multi connection to a sensitive system on a computer network. SSL based on RSA is generally used as a key distribution protocol. By reducing two times encryption/decryption procedures to one time and using ECC algorithm this protocol is faster than SSL. Analyzing the key distribution time on a normal PC experiment, we show that this could be practically used in real world without a hardware implementation.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1071-1073
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• 2000

The use of HDL(Hardware Description Language) is now central to the ASIC(Application Specific Integrated Circuit). HDL-based ASIC can simplify the process of development and has a competition in market because it reduce the consuming time for the design of IC(Integrated circuit) in system level. Therefore, the development of power electronics system on chip (SOC), to design microcontroller and switching logic as one chip, is required extremely for the purpose of having reliability and low cost in power electronics which is based on switching elements. The major application of SOC is variable converter, active filter inverter for induction motor. UPS and power supply with a view to reducing electro-magnetic pollution.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.5
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• pp.295-304
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• 2003

In this paper, we proposed a hardware-oriented Genetic Algorithm Processor(GAP) based on subpopulation architecture for high-performance convergence and reducing computation time. The proposed architecture was applied to enhancing population diversity for correspondence to premature convergence. In addition, the crossover operator selection and linear ranking subpop selection were newly employed for efficient exploration. As stochastic search space selection through linear ranking and suitable genetic operator selection with respect to the convergence state of each subpopulation was used, the elapsed time of searching optimal solution was shortened. In the experiments, the computation speed was increased by over $10\%$ compared to survival-based GA and Modified-tournament GA. Especially, increased by over $20\%$ in the multi-modal function. The proposed Subpop GA processor was implemented on FPGA device APEX EP20K600EBC652-3 of AGENT 2000 design kit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Journal of information and communication convergence engineering
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• v.17 no.4
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• pp.279-284
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• 2019

This paper presents processing-node status-based message scattering and gathering algorithms for multi-processor systems on chip to reduce the communication time between processors. In the message-scattering part of the message-passing interface (MPI) scatter function, data transmissions are ordered according to the proposed linear algorithm, based on the processor status. The MPI hardware unit in the root processing node checks whether each processing node's status is 'free' or 'busy' when an MPI scatter message is received. Then, it first transfers the data to a 'free' processing node, thereby reducing the scattering completion time. In the message-gathering part of the MPI gather function, the data transmissions are ordered according to the proposed linear algorithm, and the gathering is performed. The root node receives data from the processing node that wants to transfer first, and reduces the completion time during the gathering. The experimental results show that the performance of the proposed algorithm increases at a greater rate as the number of processing nodes increases.