• Title/Summary/Keyword: Reduced-width multiplier

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Analysis of Reduced-Width Truncated Mitchell Multiplication for Inferences Using CNNs

  • Kim, HyunJin
    • IEMEK Journal of Embedded Systems and Applications
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    • v.15 no.5
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    • pp.235-242
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    • 2020
  • This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

Design of Low-error Fixed-width Modified Booth Multiplier Using Booth Encoder Outputs (Booth 인코더 출력을 이용한 저오차 고정길이 modified Booth 곱셈기 설계)

  • 조경주;김원관;정진균
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.2C
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    • pp.298-305
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    • 2004
  • This paper presents an error compensation method for a fixed-width modified Booth multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 40% reduction in area and power consumption of a multiplier compared with the ideal multiplier.

A module generator for variable-precision multiplier core with error compensation for low-power DSP applications (저전력 DSP 응용을 위한 오차보상을 갖는 가변 정밀도 승산기 코어 생성기)

  • Hwang, Seok-Ki;Lee, Jin-Woo;Shin, Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2A
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    • pp.129-136
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    • 2005
  • A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

Maximum Error Reduction for Fixed-width Modified Booth Multipliers Based on Error Bound Analysis (오차범위 분석을 통한 고정길이 modified Booth 곱셈기의 최대오차 감소)

  • Cho, Kyung-Ju;Chung, Jin-Gyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.10 s.340
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    • pp.29-34
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    • 2005
  • The maximum quantization error has serious effect on the performance of fixed-width multipliers that receive W-bit inputs and produce W-bit products. In this paper, we analyze the error bound of fixed-width modified Booth multipliers. Then, the estimation method for the number of additional columns for fixed-width multipliers is proposed to limit the maximum quantization error within a desired bound. In addition, it is shown that our methodology can be extended to reduced-width multipliers. By simulations, it is shown that the proposed error analysis method is useful to the practical design of fixed-width modified Booth multipliers.

A Efficient Architecture of MBA-based Parallel MAC for High-Speed Digital Signal Processing (고속 디지털 신호처리를 위한 MBA기반 병렬 MAC의 효율적인 구조)

  • 서영호;김동욱
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.7
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    • pp.53-61
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    • 2004
  • In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

Design and Performance Evaluation of Small Size Counting and Imaging Gamma Probe System (소형 계수용 및 영상용 감마프로브 시스템의 설계와 성능평가)

  • Yang, Myo-Geun;Kwark, Cheol-Eun;Sim, yong-Geol;Kim, Hee-Joung;Choi, Yong;Chung, Jung-Key;Lee, Myung-Chul;Koh, Chang-Soon
    • Journal of Biomedical Engineering Research
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    • v.18 no.3
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    • pp.291-299
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    • 1997
  • As a microimaging device detecting gamma rays emitted from small lesions or tumors during operation, the intraoperative surgical probe has been proposed and is now under development. We have designed a multipurpose portable gamma prove system and evaluated the performance both for the absolute counting purpose of residual radioactivities and for the localizing capability of gamma events using the NaI(Tl) crystal and two types of photomultiplier tubes(PMTs). Counting efficiencies in the range of routine clinical use of radiation dose were measured using the assembly of single channel PMTs and 0.5 inch thick NaI(Tl) crystal of 1 inch diameter. The positioning of gamma events for imaging purpose requires the multiple channel PMTs with appropriate positioning electronics. We have designed a simple and reliable positioning circuit based on the concept of modified Anger. In preliminary experiments using the multiple channel PMT of 3 inch diameter and the dim lighth source, we were able to trace and localize the correct position with reduced positioning error by the use of two multiplier/divider chipset and simplified peripherals. The energy resolutions for the counting gamma probe measured as full width at half maximum(FWHM) for Cs-137, F-18, Tc-99m were 12%, 13%, and 36%, respectively. The spatial resolution for the imaging gamma probe measured as FWHM for green LED was 2.9 mm. The results indicate that the currently developing probe is very promising and could be very useful for many applications in nuclear medicine. Future studies will include developing collimators, improving interface hardwares, and evaluating the system with clinical data.

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