• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1743-1751
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• 2016

The increasing demand for high voltage DC grids resulting from the continuous installation of offshore wind farms in the North Sea has led to the concept of multi-terminal direct current (MTDC) grids, which face some challenges. Power (current) flow control is a challenge that must be addressed to realize a reliable operation of MTDC grids. This paper presents a reduced switch count topology of a current flow controller (CFC) for power flow and current limiting applications in MTDC grids. A simple control system based on hysteresis band current control is proposed for the CFC. The theory of operation and control of the CFC are demonstrated. The key features of the proposed controller, including cable current balancing, cable current limiting, and current nulling, are illustrated. An MTDC grid is simulated using MATLAB/SIMULINK software to evaluate the steady state and dynamic performance of the proposed CFC topology. Furthermore, a low power prototype is built for a CFC to experimentally validate its performance using rapid control prototyping. Simulation and experimental studies indicate the fast dynamic response and precise results of the proposed topology. Furthermore, the proposed controller offers a real solution for power flow challenges in MTDC grids.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1519-1528
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• 2017

The paper proposes a well structured, component count waned single phase multilevel inverter (MLI) topology, which drives three different modules viz. Stipulation Based Sources Insertion (SBSI) module, Level Count Increasing (LCI) module and Inter-Linking H-Bridge (ILHB) module. The SBSI module confronts the number of basic sources needed in series/parallel to achieve required magnitude for any particular level. The LCI possesses an offsetting dc source and opuses to increase the number of levels and the ILHB module links the SBSI and LCI modules. A developed Hybrid Pulse Width Modulation (HPWM) strategy has PWM pulses for the switches of LCI module while the switches of the remaining two modules function at fundamental switching frequency. A fifteen level version of the proposed stipulation based sources insertion MLI (SBSIMLI) topology is simulated in MATLAB R2010a and a prototype of the similar specifications is constructed to validate the performance by experimental results. The comparison between the developed SBSIMLI topology and the competent topologies shows many interesting facts.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.229-236
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• 2017

This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

• Journal of Power Electronics
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• v.19 no.3
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• pp.676-690
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• 2019

This paper presents a switched capacitor (SC) based bidirectional dc-dc converter topology for high voltage gain applications. The proposed converter is able to operate with multiple integral voltage conversion ratios based on user input. The architecture of a user-friendly, inductor-less multi-voltage-gain bidirectional dc-dc converter is proposed in this study. The inductor-less or magnetic-less design of the proposed converter makes it effective in higher temperature applications. Furthermore, the proposed converter has a reduced component count and lower voltage stress across its switches and capacitors when compared to existing SC converters. An output impedance analysis of the proposed converter is presented and compared with popular existing SC converters. The proposed converter is simulated in the OrCAD PSpice environment and the obtained results are presented. A 200 W hardware prototype of the proposed SC converter has been developed. Experimental results are presented to validate the efficacy of the proposed converter.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1314-1321
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• 2014

A new simplified topology for a dynamic voltage restorer (DVR) based on direct converter with a reduced number of switches is presented. The direct converter is fabricated using only three bi-directional controlled switches. The direct converter is connected between the grid and center-tapped series transformer. The center-tapped series transformer is used to inject the compensating voltage synthesized by the direct converter. The DVR can properly compensate for long-duration, balanced, and unbalanced voltage sag and swell by taking power from the grid. The switches are driven by ordinary pulse width modulation signals. Simulation and hardware results validate the idea that the proposed topology can mitigate sag of 50% and swell of unlimited quantity.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of Power Electronics
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• v.11 no.5
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• pp.677-687
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• 2011

In this paper a cycloconverter-type high frequency transformer link inverter with a reduced switch count is analyzed and designed. The proposed topology consists of an H-bridge inverter at the transformer's primary side and a cycloconverter with three bidirectional switches at the secondary. All of the switches of the cycloconverter operate in non-resonant zero voltage and zero current switching modes. To overcome a high voltage surge problem resulting from the transformer leakage inductance, phase angle control based on natural commutation is employed. The effectiveness of the proposed inverter is verified by constructing s 750W prototype. Experimentally, the inverter is able to supply a near sinusoidal output voltage with a total harmonic distortion of less than 1%. For comparison, a PSpice simulation of the inverter is also carried out. It was found that the experimental results are in very close agreement with the simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.194-198
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• 2021

LoRa is a physical layer technology that is designed to provide a reliable long-range communication with introducing CSS and with introducing a loco parentis tree network. Since a leaf can utilize multiple parents at the same time with a single transmission, PDR increases logarithmically as the number of gateways increases. Because of the ALOHA-like MAC of LoRa, however, the PDR degrades even under the loco parentis tree topology similarly to the single-gateway environment. Our proposed method is aimed to achieve SDMA approach to reuse the same frequency in different areas. For that purpose, it elaborately controls each TxPower of the senders for each message in concurrent transmission to survive the collision at each different gateway. The gain from this so-called capture effect increases the capacity of resource-hungry LPWAN. Compared to a typical collision-free controlled-access scheme, our method outperforms by 10-35% from the perspective of the total count of the consumed time slots. Also, due to the power control mechanism in our method, the energy consumption reduced by 20-40%.