• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.10a
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• pp.173-176
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• 2007

The characteristics of the tool system give many effects into the costs and qualities for the finished components. This study proposes a new method for manufacturing of high manufacturing productivity, production process reduction and low cost through back pressure forming. The Lock-up hub is manufactured through many processes, such as upsetting($1^{st}$ Forming), piercing, direct extrusion($2^{nd}$ Forming), final sizing process($3^{rd}$ Forming). In this study, process design for closed-die forging of a Lock-up hub used for a component of automobile transmission was made using three-dimensional finite element simulations, and the strain distributions and velocity distributions are investigated through the post processor. The rigid-plastic finite-element method for back pressure forging has been used in order to reduce development time and die cost. Using the FEM simulation, we found the optimum value of back pressure. The prototypes of Lock-up hub parts were forged into the net-shape. In the experiment, lead precision of tooth are measured by the CCMM(Contact Coordinate Measuring Machine). The dimensional accuracy of forged part was improved up to the 40% when back press was applied.

• Transactions of Materials Processing
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• v.17 no.2
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• pp.124-129
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• 2008

Net shape forging technologies give many effects into the costs and qualities for the finished products. So, the studies to reduce the additional machining amount are very important in forging industry. Specially, there are two main topics in cold forging industry, such as, tool life and precision forging. In this study, new forging technique was proposed to eliminate the machining process for fixing up the length and improve the lead accuracy of gear. The luck-up hub is manufactured through many processes, such as upsetting, piercing and direct extrusion. The gear is formed in direct extrusion process; however, lead accuracy of the gear is over allowance limit. Therefore, the additional sizing process must be added. In this study, process design for closed-die forging of a lock-up hub used for a component of automobile transmission was made using three-dimensional finite element simulations, and the strain distributions and velocity distributions are investigated through the post processor. The rigid-plastic finite-element method for back pressure forging has been used in order to reduce development time and die cost. Using the FEM simulation, we found the optimum value of back pressure. The prototypes of lock-up hub parts were forged into the net-shape. In the experiment, lead precision of tooth are measured by the CCMM(Contact Coordinate Measuring Machine). The dimensional accuracy of forged part was improved up to the 40% when back press was applied.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• ETRI Journal
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• v.28 no.4
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• pp.435-443
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• 2006

This paper presents an efficient carrier recovery algorithm combined with a turbo-coding technique in a mobile communication system. By using a block turbo code made up of independently decodable block codes, we can efficiently recover the fast time-varying carrier phase as well as correct channel errors. Our simulation results reveal that the proposed scheme can accommodate mobiles with high speed, and at the same time can reduce the number of iterations to lock the phase.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.4
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• pp.635-641
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• 2006

On the wireless-communication between Electronic Tag of RFID system and Reader, there are some existing problems with weaknesses of security such as spoofing, replay, traffic analysis, position tracking, etc., in the established hash-lock related algorithm. This paper has presented the comparison and analysis of the established hash-lock related algorithm for privacy and in order to make up for this, also suggested a new security authentication algorithm based on hash which has an authentication protocol and creates hash function by using random numbers received from the reader on real-time and every session. The algorithm suggested is able to make RFID wireless authentication system offer a several of usefulness and it has an advantage to reduce the amount of calculations compared to established algorithm. It also uses just the tags needed among a lot of tags around which are expected later and it is expected to reduce a responsibility of the server by ending unnecessary tags' action with time based.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.69-75
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• 2007

On the wireless communication between RFID Tag and Reader, there are some existing problems with weaknesses of security such as spoofing, replay, traffic analysis, position tracking, etc., in the established hash lock related algorithm. This paper has presented the comparison and analysis of the established hash lock related algorithm for privacy and in order to make up for this, also suggested a new security authentication algorithm based on hash which has an authentication protocol and creates hash function by using random numbers received from the reader on real time and every session. The algorithm suggested here can offer a several of usefulness for RFID authentication system and it has an advantage to reduce the amount of calculations compared to established algorithm. It also uses the tags needed among a lot of tags around which are expected later and it is expected to reduce a responsibility of the server by ending unnecessary tags' operation with time based.

• Proceedings of the KIEE Conference
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• summer
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• pp.563-565
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• 2004

It is expected to reduce stresses to components of high voltage circuit breaker and transferred switching surge from power system by applying controlled switching technique to high voltage system. This technique has at ready been applied in advanced countries. In this paper, basic principle of controlled switching technique is set up and a device to realize this technique is under developing. Controlled switching device will be improved by applying a method minimizing errors of operating time and by adopting compensation function relative to changes of ambient/operating condition.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.