• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1836-1840
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• 2003

This paper, we propose a new phase-locked loop (PLL) system with the controllable output phase, independent from the output frequency, and lock-up time. This PLL system has a dual control loop is described, the inner loop greatly improved VCO characteristic such as faster speed response as well as higher operation bandwidth, to minimize the effect of the VCO noise and the power supply variation and also get better linearity of VCO output. The main loop is the heart of this PLL which greatly improved the output frequency instability due to the external high frequency noise coupling to the input reference frequency also the main loop can control the output phase, independent from the output frequency, and reduce the lock-up time of the step frequency response. The experimental results confirm the validity of the proposed strategy.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2007년도 추계학술대회 논문집
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• pp.173-176
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• 2007

The characteristics of the tool system give many effects into the costs and qualities for the finished components. This study proposes a new method for manufacturing of high manufacturing productivity, production process reduction and low cost through back pressure forming. The Lock-up hub is manufactured through many processes, such as upsetting($1^{st}$ Forming), piercing, direct extrusion($2^{nd}$ Forming), final sizing process($3^{rd}$ Forming). In this study, process design for closed-die forging of a Lock-up hub used for a component of automobile transmission was made using three-dimensional finite element simulations, and the strain distributions and velocity distributions are investigated through the post processor. The rigid-plastic finite-element method for back pressure forging has been used in order to reduce development time and die cost. Using the FEM simulation, we found the optimum value of back pressure. The prototypes of Lock-up hub parts were forged into the net-shape. In the experiment, lead precision of tooth are measured by the CCMM(Contact Coordinate Measuring Machine). The dimensional accuracy of forged part was improved up to the 40% when back press was applied.

• 소성∙가공
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• 제17권2호
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• pp.124-129
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• 2008

Net shape forging technologies give many effects into the costs and qualities for the finished products. So, the studies to reduce the additional machining amount are very important in forging industry. Specially, there are two main topics in cold forging industry, such as, tool life and precision forging. In this study, new forging technique was proposed to eliminate the machining process for fixing up the length and improve the lead accuracy of gear. The luck-up hub is manufactured through many processes, such as upsetting, piercing and direct extrusion. The gear is formed in direct extrusion process; however, lead accuracy of the gear is over allowance limit. Therefore, the additional sizing process must be added. In this study, process design for closed-die forging of a lock-up hub used for a component of automobile transmission was made using three-dimensional finite element simulations, and the strain distributions and velocity distributions are investigated through the post processor. The rigid-plastic finite-element method for back pressure forging has been used in order to reduce development time and die cost. Using the FEM simulation, we found the optimum value of back pressure. The prototypes of lock-up hub parts were forged into the net-shape. In the experiment, lead precision of tooth are measured by the CCMM(Contact Coordinate Measuring Machine). The dimensional accuracy of forged part was improved up to the 40% when back press was applied.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• ETRI Journal
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• 제28권4호
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• pp.435-443
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• 2006

This paper presents an efficient carrier recovery algorithm combined with a turbo-coding technique in a mobile communication system. By using a block turbo code made up of independently decodable block codes, we can efficiently recover the fast time-varying carrier phase as well as correct channel errors. Our simulation results reveal that the proposed scheme can accommodate mobiles with high speed, and at the same time can reduce the number of iterations to lock the phase.

• 한국산학기술학회논문지
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• 제7권4호
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• pp.635-641
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• 2006

RFID 시스템의 전자 태그, 리더 간의 무선 통신에서, 기존의 해쉬-락 관련 알고리즘은 스푸핑, 재전송, 트래픽 분석 및 위치 추적 등 보안상의 취약점이 존재한다. 본 논문에서는 개인정보 보호를 위한 기존의 해쉬-락 관련 알고리즘을 비교, 분석하였으며 이를 보완하기 위하여 실시간과 매 세션마다 리더로부터 수신한 난수를 이용하여 해쉬 함수를 생성하고 인증 프로토콜을 가지는 새로운 해쉬기반 보안 인증 알고리즘을 제안하였다. 제안한 알고리즘은 RFID 무선 인증 시스템에서 다양한 유용성을 제공할 수 있으며, 기존의 알고리즘에 비해 계산량을 절감할 수 있는 장점이 있다. 또한 추후 예상되는 주변의 수많은 태그중 필요한 태그만 선별하여 사용하며, 시간 기반으로 불필요 태그의 동작을 종료시켜 서버부담을 줄이는 방법이 될 것으로 기대된다.

• 한국컴퓨터정보학회논문지
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• 제12권4호
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• pp.69-75
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• 2007

RFID 시스템의 전자 Tag, Reader 간의 무선 통신에서, 기존의 해쉬-락 관련 알고리즘은 스푸핑, 재전송, 트래픽 분석 및 위치 추적등 보안상의 취약점이 존재한다. 본 논문에서는 개인정보 보호를 위한 기존의 해쉬-락 관련 알고리즘을 비교, 분석하였으며 이를 보완하기 위하여 실시간과 매 세션마다 리더로부터 수신한 난수를 이용하여 해쉬 함수를 생성하고 인증 프로토콜을 가지는 새로운 해쉬 기반 보안 인증 알고리즘을 제안하였다. 제안한 알고리즘은 RFID 무선 인증 시스템에서 다양한 유용성을 제공할 수 있으며, 기존의 알고리즘에 비해 계산량을 절감할 수 있는 장점이 있다. 또한 추후 예상되는 주변의 수많은 태그 중 필요한 태그만 선별하여 사용하며, 시간 기반으로 불필요 태그의 동작을 종료시켜 서버부담을 줄이는 방법이 될 것으로 기대된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.563-565
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• 2004

It is expected to reduce stresses to components of high voltage circuit breaker and transferred switching surge from power system by applying controlled switching technique to high voltage system. This technique has at ready been applied in advanced countries. In this paper, basic principle of controlled switching technique is set up and a device to realize this technique is under developing. Controlled switching device will be improved by applying a method minimizing errors of operating time and by adopting compensation function relative to changes of ambient/operating condition.

• 대한전자공학회논문지TC
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• 제42권7호
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• pp.35-40
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• 2005

본 논문에서는 900MHz 대역 중저속 무선 통신용 칩에 이용되는 3차 ${\Delta}{\sum}$ modulator를 사용한 Fractional-N PLL 주파수 합성기를 설계 및 제작하였다 우수한 위상노이즈 특성을 얻기 위해 노이즈 특성이 좋은LC VCO를 사용하였다. 그리고 고착시간을 줄이기 위해서 Charge Pump의 펌핑 전류를 주파수 천이 값에 따라 조절할 수 있도록 제작하였고 PFD의 참조 주파수를 3MHz까지 높였다. 또한 참조 주파수를 높이는 동시에 PLL의 최소 주파수 천이 간격을 10KHz까지 줄일 수 있도록 하기위하여 36/37 Fractional-N 분주기를 제작하였다. Fractional Spur를 줄이기 위해서 3차 ${\Delta}{\sum}$ modulator를 사용하였다. 그리고 VCO, Divider by 8 Prescaler, PFD, 및 Charge Pump는 0.25um CMOS공정으로 제작되었으며, 루프 필터는 외부 컴포넌트를 이용한 3차RC 필터로 제작되었다. 그리고 Fractional-N 분주기와 3차 ${\Delta}{\sum}$ modulator는 VHDL 코드로 작성되었으며 Xilinx Spartan2E을 사용한 FPGA 보드로 구현되었다. 측정결과 PLL의 출력 전력은 약 -11dBm이고, 위상노이즈는 100kHz offset 주파수에서 -77.75dBc/Hz이다. 최소 주파수 간격은 10kHz이고, 최대 주파수 천이는 10MHz이고, 최대 주파수 변이 조건에서 고착시간은 약 800us이다.