• Convergence Security Journal
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• 제13권6호
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• pp.3-9
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• 2013

With the rapidly changing information communication environment and development of technologies, the informati on networks are evolved from traditional fixed form to an active variable network that flexible large variety of data can be transferred. To reflect the needs of users, the next generation using DWDM (Dense Wavelength Division M ultiplexing) transmission system and OXC (Optical Cross Connect) form a dynamic network. After that GMPLS (Ge neralized Multi-Protocol Label Switching) can be introduced to dynamically manage and control the Reconfigurable Optical Add-drop Multiplexer (ROADM)/Photonic Cross Connect (PXC) based network. This paper propose a softw are architecture of Path Computation Element (PCE) protocol that has proposed by Internet Engineering Task Force (IETF) to path computation. The functional blocks and Application Programming Interface (API) of the PCE protoco l implementation are also presented.

• Journal of Industrial Convergence
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• 제20권5호
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• pp.77-82
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• 2022

Evaluating methods for software asset have been made based on subjective evaluation criteria. In this study, we try to evaluate the usability of complex assets obtained from the previous measurement of the complexity of the asset management system. The evaluation used a scale provided by measuring logical complexity to measure the complexity of the asset, and evaluated the relationship with the usability of the software asset by measuring the index related to reusability. Therefore, it can be seen that HVs maintain a constant ratio according to the composition of various assets for the two types of assets and maintain the applied consistency. Therefore, it can be determined that an asset optimized in terms of usability can be applied consistently in the architectural design process while securing as much diversity as possible.

• The KIPS Transactions:PartA
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• 제9A권4호
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• pp.459-466
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• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제12권3호
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• pp.485-492
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• 2008

Computers used fer light-weight computing environments are considerably limited in resources and performance running in ubiquitous environment. Because of the limited resources, it is difficult to apply existing security technologies to the light-weight computers. In this paper, light-weight security software is implemented using RC-5 encryption and SHA-1 authentication algorithm which is appropriate for light-weight computing environments. The design of components based on security software of a light-weight computer application and the test-bed for security software are presented. The simulation verifies the correctness of the security software. The architecture of the light-weight and reconfigurable security software for light-weight computer applications is proposed. The proposed security software is small size and provides reconfigurable security library based on the light-weight component and the software manager that configures software platform is loaded with the library at the time it is needed.

• Journal of Ubiquitous Convergence Technology
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• 제2권2호
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• pp.59-66
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• 2008

In this study, Software Defined Radio (SDR) technology-based digital filterbank architecture applicable to a multiple-channel processing system such as a wireless mobile communication system using Code Division Multiple Access (CDMA) technology is proposed. The technique includes a micro-processor to redesign Finite Impulse Response (FIR) filter coefficients according to specific system information and to download the filter coefficients to one digital Band Pass Filter (BPF) to reconfigure another system. The feasibility of the algorithm is verified by computer simulation and by implementing a multiple-channel signal generator that is reconfigurable to other system profiles, including those of a Wideband Code Division Multiple Access (WCDMA) system and a CDMA system.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1263-1266
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• 2003

One of the hardest problems in implementation of digital neural network are extension of synapses and programmability for relocating neurons. This paper Proposes a new hardware structure to solve these problems. The proposed structure can reconfigure network connections without alteration of basic design, and extend number of synapses attached to one neuron. Also, it is possible to extend the number of neurons and layers by connecting many MPUs(Modular Processing Unit). Generality and extensibility are verified by composing various kinds of Perceptorn and Kohonen networks using the architecture proposed in this paper and the verification performances compares well with HDL simulation results as well as the results of C modelling.

• Smart Structures and Systems
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• 제3권1호
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• pp.69-88
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• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

• Journal of KIISE:Information Networking
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• 제34권2호
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• pp.81-87
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• 2007

This paper proposes architecture of Linux-based Network Traffic Control Test-bed (NTCT) that easily implements reconfigurable network environment. The proposed NTCT consists of traffic generator that uses the simulation results of NS2 simulator, traffic controller using Linux kernel, and traffic monitor. This paper also includes the analysis example using the proposed NTCT.

• Journal of Communications and Networks
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• 제18권2호
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• pp.135-149
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• 2016

Cloud radio access network (C-RAN) refers to the virtualization of base station functionalities by means of cloud computing. This results in a novel cellular architecture in which low-cost wireless access points, known as radio units or remote radio heads, are centrally managed by a reconfigurable centralized "cloud", or central, unit. C-RAN allows operators to reduce the capital and operating expenses needed to deploy and maintain dense heterogeneous networks. This critical advantage, along with spectral efficiency, statistical multiplexing and load balancing gains, make C-RAN well positioned to be one of the key technologies in the development of 5G systems. In this paper, a succinct overview is presented regarding the state of the art on the research on C-RAN with emphasis on fronthaul compression, baseband processing, medium access control, resource allocation, system-level considerations and standardization efforts.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제8권5호
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• pp.1069-1075
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• 2007

New BESA cryptographic algorithm is suitable network environment and wire/wireless communication network, on implement easy, security rate preservation, scalable & reconfigurable. Though proposed algorithm strengthens security vulnerability of TCP/IP protocol and keep security about many user as that have authentication function in network environment, there is important purpose. So that new BESA cryptographic algorithm implemented by hardware base cryptosystem and en/decryption is achieved at the same time, composed architecture.