• ETRI Journal
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• v.29 no.1
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• pp.79-88
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• 2007

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.28-36
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• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• ETRI Journal
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• v.31 no.5
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• pp.545-553
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• 2009

String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on-chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.6
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• pp.539-545
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• 2011

This paper describes an intelligent service robot system for managing a store in an unmanned environment. The robot can be a good replacement for humans because it is possible to work all day and to remember lots of information. We design a system architecture for configuring many intelligent functions of intelligent service robot system which consists of four layers; a User Interaction Layer, a Behavior Scheduling Layer, a Intelligent Module Layer, and a Hardware Layer. We develop an intelligent service robot 'Part Timer' based on the designed system architecture. The 'Part Timer' has many intelligent function modules such as face detection-recognition-tracking module, speech recognition module, navigation module, manipulator module, appliance control module, etc. The 'Part Timer' is possible to answer the phone and this function gives convenient interface to users.

• The KIPS Transactions:PartC
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• v.17C no.1
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• pp.89-98
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• 2010

In current digital broadcasting systems, GEM(Globally Executable MHP)-based middlewares such as MHP(Multimedia Home Platform), OCAP(OpenCable Application Platform), ACAP(Advanced Common Application Platform) are the norm. Despite much of the common characteristics shared, such as MPEG-2 and DSM-CC(Digital Storage Media-Command and Control) protocols, the information and data structures they need are slightly different, which results in incompatibility issues. In this paper, in line with an effort to develop an integrated DTV middleware, we propose a general-purpose, reconfigurable DSM-CC architecture for supporting various standard GEM-based middlewares without code modifications. First, we identify DSM-CC components that are common and thus can be shared by all GEM-based middlewares. Next, the system is provided with middleware-specific information and data structures in the form of XML. Since the XML information can be parsed dynamically at run time, it can be interchanged either statically or dynamically for a specific target middleware. As for the performance issues, the response time and usage frequency of DSM-CC module highly contribute to the performance of STB(Set-Top-Box). In this paper, we also propose an efficient application cache management strategy and evaluate its performance. The performance result has shown that the cache strategy reflecting user preferences greatly helps to reduce response time for executing application.

• Journal of the Society of Naval Architects of Korea
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• v.48 no.6
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• pp.528-538
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• 2011

As a forming method for curved hull plates more efficient than the flame bending, mechanical bending using multi point press forming and die-less forming is discussed in this paper. the mechanical forming is a flexible manufacturing system for automatically forming of hull parts. It is especially suited to varied curved parts. This paper discusses a multiple point pressing machine composed of a pair of reconfigurable punches in order to achieve the rapid forming of curved hull plates using division forming and presents how forming information is obtained from the given design surface. Although the mechanical forming can be efficient in the metal forming, spring back after pressing is a phenomenon which must be carefully considered when quantifying the process variables. If the spring back is not accurately controlled, the fabricated shell plate cannot meet assembly tolerance. This paper describes the principles to calculate the proper stroke of each punch at the divided areas. the strokes are determined by an iterative process of sequential pressing and spring back compensation from an unfolded flat shape to its given design surface. FEA(finite element analysis) is used to simulate the spring back of the plate and the IDA(iterative displacement adjustment) method adjusts the offset of pressing punches from the deformation results and the design surface. The shape deviations of two surfaces due to spring back are compensated by integrated system using FEA and IDA method. For the practical application, It is aimed to develop an integrated system that can automatically perform the compensation process and calculate strokes of punches of the double sides' reconfigurable multiple-press machine and some experimental results obtained with mechanical bending are presented.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.667-670
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• 2004

In this paper, we have presented the improved IF transceiver architecture and the implementation and experimental results on re-configurable transceiver based on digital IF for multiple wideband OFDM/TDD base stations for high-speed portable internet-service in which is issued Korea. The implemented IF transceiver has been designed to support multiple frequency allocations and multiple standards by only modifying the programmable software not its hardware like as the software-defined-radio concept. Also, the digital complex quadrature modulation technique has been used for the digital IF transmitter, which is able to combine multiple frequency bands in digital processing block not RF block and to reject the image frequency signals. And the bandpass sampling technique has been used for the digital IF receiver to reduce the sampling rate of ADC. This paper has shown the experiment results on the frequency response and constellation on the base-station implemented using the modified IEEE 802.16a/e physical layer channel structure based on OFDM/TDD.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.3
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• pp.9-17
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• 2020

In this paper, as part of the research for the infrastructure of very high flexible and reconfigurable data center using very high speed crossbar switches, we developed a simulator that can model two and three dimensional connection structure of switches with an efficient control algorithm using software defined network and verified the functions and analyzed the performance accordingly. The simulator consists of a control module and a switch module that was coded using Python language based on the Mininet and Ryu Openflow frameworks. The control module dynamically controls the operation of switching cells using a shortest multipath algorithm to calculate efficient paths adaptively between configurable computing resources. Performance analysis by using the simulator shows that the three-dimensional switch architecture can accommodate more hosts per port and has about 1.5 times more successful 1:n connections per port with the same number of switches than the two-dimensional architecture. Also simulation results show that connection length in a 3-dimensional way is shorter than that of 2-dimensional way and the unused switch ratio in a 3-dimensional case is lower than that of 2-dimensional cases.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.153-160
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• 1996

In this paper, we propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNN's). DTCNN's have the locality and the translation invariance in the templates which determine the patterns of the connection between the cells. Using distributed arithmetic (DA) and the characteristics of DTCNN, we propose a simple implementation of DTCNN. The bus width in the cell-to-cell interconnection is reduced to one bit because of DA's bitwise operation. We implemented the reconfigurable architecture of DTCNN using programmable FPGA.