• IEMEK Journal of Embedded Systems and Applications
• /
• v.6 no.6
• /
• pp.345-359
• /
• 2011

In high performance embedded systems, the use of multiple on-chip memories is an essential architectural feature for exploiting inherent parallelism in multimedia applications. This feature allows multiple data accesses to be executed in parallel. However, it remains difficult to effectively exploit of multiple on-chip memories. The successful use of this architecture strongly depends on how to efficiently detect and exploit memory parallelism in target applications. In this paper, we propose a technique based on a linear array access descriptor [1], which is generated from profiled data, to detect and exploit memory parallelism. The proposed technique tackles an array reorganization problem to maximize memory parallelism in multimedia applications. We present preliminary experiments applying the proposed technique onto a representative coarse grained reconfigurable array processor (CGRA) with multimedia kernel codes. Our experimental results demonstrate that our technique optimizes data placement by putting independent data on separate storage. The results exhibit 9.8% higher performance on average compared to the existing method.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2009.04a
• /
• pp.875-876
• /
• 2009

최근에 응용프로그램의 복잡도가 증가함에 따라 이를 빠르게 처리하기 위하여 각종 멀티미디어 SoC에서 Coarse Grained Reconfigurable Architecture (CGRA)들이 사용되고 있다. CGRA가 제공하는 병렬성을 극대화하기 위한 많은 어플리케이션 매핑 알고리즘이 연구되어 왔으나 CGRA에서 소모되는 전력을 줄이기 위한 노력은 거의 없는 상태이다. 이러한 문제를 극복하기 위해 본 논문에서는 기존의 매핑 알고리즘을 기반으로 누설전력을 줄이기 위한 방법에 대해 다루고자 한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.11a
• /
• pp.24-27
• /
• 2011

재구성형 프로세서는 높은 성능과 낮은 전력 소모, 재구성이 가능하다는 점에서 갈수록 높아지는 모바일 및 소형 전자기기 시장의 요구 조건을 충족시키기에 적합한 특성을 가지고 있다. 이 논문에서는 아키텍처 명세 언어인 SoarDL 언어를 확장하여 재구성형 프로세서를 효과적으로 기술할 수 있는 방법과 함께, 이를 바탕으로 재구성형 프로세서를 위한 컴파일러를 생성할 수 있는 방안을 제시한다.

• Journal of the Korea Society of Computer and Information
• /
• v.14 no.7
• /
• pp.65-72
• /
• 2009

This paper proposed VCR cryptographic algorithm that adapted in TCP/IP protocol architecture and wire/wireless communication network environments. we implemented by hardware chip level because proposed VCR cryptographic algorithm perform scalable & reconfigurable operations into the security system. Proposed VCR cryptographic algorithm strengthens security vulnerability of TCP/IP protocol and is very profitable real-time processing and encipherment of high-capacity data and multi-user communication because there is important purpose to keep security about many user as that have variable round numbers function in network environments.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.8
• /
• pp.453-464
• /
• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.165-175
• /
• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• Journal of the Korean Society for Precision Engineering
• /
• v.29 no.4
• /
• pp.386-394
• /
• 2012

Recent trends in the flexible manufacturing systems are morphing cell control for the shop-wide production operation system and providing the integrated operation and execution system together with vendor-specific FMC/FMS platform. In these requirements, the shop-floor level operation system plays a role of coordinating the control activity of each cell, and has to provide flexibility for the complexity of mixed operations of various cells. This paper suggests a system architecture for the mixed environments of multi-cells and job shop, its corresponding enabling technologies based on comparative studies with other related studies and commercialized systems. This approach includes a process definition model considering the integration with upper BOM-BOP and external service modules, and reconfigurable device-level interface which provides dynamic interconnections with machine tools and cell controllers. The function modules and their implementation results are also described to provide the feasibility of the proposed approaches as the flexible shop-floor operation system for the multi-cell environments.

• Journal of Powder Materials
• /
• v.26 no.6
• /
• pp.528-538
• /
• 2019

The transition from "More-of-Less" markets (economies of scale) to "Less-of-More" markets (economies of scope) is supported by advances of disruptive manufacturing and reconfigurable-supply-chain management technologies. With the prevalence of cyber-physical manufacturing systems, additive manufacturing technology is of great impact on industry, the economy, and society. Traditionally, backbone structures are built via bottom-up manufacturing with either pre-fabricated building blocks such as bricks or with layer-by-layer concrete casting such as climbing form-work casting. In both cases, the design selection is limited by form-work design and cost. Accordingly, the tool-less building of architecture with high design freedom is attractive. In the present study, we review the technological trends of additive manufacturing for construction-scale additive manufacturing in particular. The rapid tooling of patterns or molds and rapid manufacturing of construction parts or whole structures is extensively explored through uncertainties from technology. The future regulation still has drawbacks in the adoption of additive manufacturing in construction industries.

• Journal of Institute of Control, Robotics and Systems
• /
• v.19 no.4
• /
• pp.328-333
• /
• 2013

Since a slight malfunction of control systems in a nuclear power plant may cause huge catastrophes, such control systems usually have multiple redundancy and reliable features, and their reliability and availability should be analyzed and verified thoroughly. This paper performed the reliability analysis of the SPLC (Safety Programmable Logic Controller) that is under developed as the control systems for the next generation nuclear power plant. One of the key features of SPLC is that it has multiple redundancy modes as faults happen, which means the reliability analysis for one fixed redundant model is not enough to analyze the reliability of SPLC. With considering this reconfigurable concept, FTA (Fault Tree Analysis) was used to capture fault-relationship among sub-modules. The analysis results show that MTTF (Mean Time to Fault) of SPLC is 45,080 hours, which is a about 4.5 times longer than the regulation, 10,000 hours.

• Journal of Digital Contents Society
• /
• v.10 no.4
• /
• pp.605-614
• /
• 2009

The software-defined radio (SDR) is a radio communication technology that can reconfigure necessary application software on a common hardware platform to deal with several kind of radio communication environment. It is necessary for a system that can control and analyze functionalities of a system in order to verify the SCA-based reconfigurable middleware platform, SCARLET that implements the SDR technology. In this paper, we propose and implement the architecture of the waveform manager that is connected with SCARLET and performs management and control functionalities. We verify the performance of the waveform manager by testing each functionality of the overall system that uses the SCARLET middleware platform.