• Title/Summary/Keyword: Rapid thermal process

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Use of a Rapid Thermal Process Technique to study on the crystallization of amorphous Si films fabricated by PECVD (PECVD 방법으로 제조된 비정질 Si 박막의 RTP를 이용한 결정화 연구)

  • Sim, C.H.;Kim, H.N.;Kim, S.J.;Kim, J.W.;Kwon, J.Y.;Lee, H.Y.
    • Proceedings of the KIEE Conference
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    • 2005.07c
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    • pp.2052-2054
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    • 2005
  • TFT-LCD requires to use poly silicon for High resolution and High integration. Thin film make of Poly silicon on the excimer laser-induced crystallization of PECVD(plasma-enhanced chemical vapor deposition)-grown amorphous silicon. In the thin film hydrogen affects to a device performance from bad elements like eruption, void and etc. So dehydrogenation prior to laser exposure was necessary. In this study, use RTP(Rapid Thermal Process) at various temperature from $670^{\circ}C$ to $750^{\circ}C$ and fabricate poly-silicon. it propose optimized RTP window to compare grain size to use poly silicon's SEM pictures and crystallization to analyze Raman curved lines.

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A Study on Improved Pore Uniformity of Nano Template Using the Rapid Thermal Processor (급속열처리를 통한 알루미나 나노템플릿의 기공 균일도 개선에 관한 연구)

  • Kim, Dong-Hee;Kim, Jin-Kwang;Kwon, O-Dae;Yang, Kea-Joon;Lee, Jae-Hyeong;Lim, Dong-Gun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.637-638
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    • 2005
  • AAO templates were fabricated using a two-step anodization process with pretreatment such as electro polishing and annealing. To reduce process time and get well-aligned pore array, rapid thermal processor by an halogen lamp was employed in vacuum state at $500^{\circ}C$ for various time. The pore array of AAO template annealed at $500^{\circ}C$ for 2 h is comparable to a template annealed in conventional furnace at $500^{\circ}C$ for 30 h. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrierlayer thickness of 25 nm, and the pore depth of $9{\mu}m$. And the pore density can be as high as $2.0\times10^{10}cm^{-2}$.

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DC Sputtering Process of 2-Dimensional Tungsten Disulfide Thin Films on Soda-Lime Glass Substrates (DC 스퍼터링을 이용한 소다라임 유리 기판상에 2차원 황화텅스텐 박막 형성 공정)

  • Ma, Sang Min;Kwon, Sang Jik;Cho, Eou Sik
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.3
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    • pp.31-35
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    • 2018
  • Tungsten disulfide($WS_2$) thin films were directly deposited by direct-current(DC) sputtering and annealed by rapid thermal processing(RTP) to materialize two-dimensional p-type transition metal dichalcogenide (TMDC) thin films on soda-lime glass substrates without any complicated exfoliation/transfer process. $WS_2$ thin films deposited at various DC sputtering powers from 80 W to 160W were annealed at different temperatures from $400^{\circ}C$ to $550^{\circ}C$ considering the melting temperature of soda-lime glass. The optical microscope results showed the stable surface morphologies of the $WS_2$ thin films without any defects. The X-ray photoelectron spectroscopy (XPS) results and the Hall measurement results showed stable binding energies of W and S and high carrier mobilities of $WS_2$ thin films.

A Study on Fracture Toughness with Thermal Aging in CF8M/SA508 Welds (CF8M과 SA508 용접재의 열화에 따른 파괴인성에 관한 연구)

  • Woo Seung-Wan;Choi Young-Hwan;Kwon Jae-Do
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.30 no.10 s.253
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    • pp.1173-1178
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    • 2006
  • In a primary reactor cooling system(RCS), a dissimilar weld zone exists between cast stainless steel(CF8M) in a pipe and low-alloy steel(SA508 cl.3) in a nozzle. Thermal aging is observed in CF8M as the RCS is exposed for a long period of time to a reactor operating temperature between 290 and $330^{\circ}C$, while no effect is observed in SA508 cl.3. The specimens are prepared by an artificially accelerated aging technique maintained for 300, 1800 and 3600 hrs at $430^{\circ}C$, respectively. The specimens for elastic-plastic fracture toughness tests are according to the process in the thermal notch is created in the heat affected zone(HAZ) of CF8M and deposited zone. From the experiments, the $J_{IC}$ value notched in HAZ of CF8M presented a rapid decrease up to 300 hours at $430^{\circ}C$ and slowly decreased according to the process in the thermal aging time. Also, the $J_{IC}$ value presented a lower value than that of the CF8M base metal. And, the $J_{IC}$ of the deposited zone presented the lowest value of all other cases.

Extension of the Site Binding Model for Ion Sensing Mechanism of ISFET and Its Application to the Hydrogen Ion Sensing $Si_3N_4$ Membrane (ISFET 이온감지기구의 Site Binding 모형 확장과 그 $Si_3N_4$ 수소이온 감지막에의 적용)

  • Seo, Hwa-Il;Kwon, Dae-Hyuk;Lee, Jong-Hyun;Sohn, Byung-Ki
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.11
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    • pp.1358-1366
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    • 1988
  • The dual dielectric films have been grown on single-crystalline silicon substrates with the thickness ranging from 125A to 180A at various gas and temperature conditions by using rapid thermal process that included independent nitridation step. The film characteristics and their dependence on the contents of the hydrochloric gas and the processing time have been studied. By the addition of the hydrochloric gas, the initial oxide thickness was significantly changed, but after sequential nitridation processes the thickness of the films was nevertheless a little bit varied within 10A. All the samples of the dual dielectric films show the increased breakdown voltages in proportion to the additive contents of the hydrochloric gas and also show the higher breakdown strengths than the thermal oxide and nitrided oxide films grown by the conventional furnance process or the rapid thermal nitridation process that was composed of the dependent nitridation cycles.

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Effects of the Contents of Hydrochloric Gas on the Electrical Properties of the RTO/RTN Dual Dielectric Films (HCI 첨가에 의한 RTO/RTN 이중 절연박막의 전기적 특성 변화)

  • Kim, Youn-Tae;Park, Sung-Ho;Bae, Nam-Jin;Kim, Bo-Woo;Ma, Dong-Sung
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.11
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    • pp.1350-1357
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    • 1988
  • The dual dielectric films have been grown on single-crystalline silicon substrates with the thickness ranging from 125A to 180A at various gas and temperature conditions by using rapid thermal process that included independent nitridation step. The film characteristics and their dependence on the contents of the hydrochloric gas and the processing time have been studied. By the addition of the hydrochloric gas, the initial oxide thickness was significantly changed, but after sequential nitridation processes the thickness of the films was nevertheless a little bit varied within 10A. All the samples of the dual dielectric films show the increased breakdown voltages in proportion to the additive contents of the hydrochloric gas and also show the higher breakdown strengths than the thermal oxide and nitrided oxide films grown by the conventional furnance process or the rapid thermal nitridation process that was composed of the dependent nitridation cycles.

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Shallow Junction Device Formation and the Design of Boron Diffusion Simulator (박막 소자 개발과 보론 확산 시뮬레이터 설계)

  • Han, Myoung Seok;Park, Sung Jong;Kim, Jae Young
    • 대한공업교육학회지
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    • v.33 no.1
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    • pp.249-264
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    • 2008
  • In this dissertation, shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes and a new simulator is designed to model boron diffusion in silicon. This simulator predicts the boron distribution after ion implantation and annealing. The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a RTA(Rapid Thermal Annealing) and a FA(Furnace Annealing) process. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of sheet resistance and the simulator reproduced experimental data successfully. Therefore, proposed diffusion simulator and FA+RTA annealing method was able to applied to shallow junction formation for thermal budget. process.

A Study on Electrical Properties of Sol-gel Derived Bi3.25La0.75Ti3O12 Thin Films by Rapid Thermal Annealing (Sol-gel법으로 제조한 강유전성 Bi3.25La0.75Ti3O12박막의 급속열처리에 따른 전기적 특성에 관한 연구)

  • 이인재;김병호
    • Journal of the Korean Ceramic Society
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    • v.40 no.12
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    • pp.1189-1196
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    • 2003
  • Ferroelectric B $i_{3.25}$L $a_{0.75}$ $Ti_3$ $O_{12}$ (BLT) solution was synthesized by sol-gel process. BLT thin films were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. In this experiments, Bi(TMHD)$_3$, La(III)2-Methoxyethoxide, and Ti(IV) i-propoxide were used as starting materials, which were dissolved in 2-Methoxyethanol. Rapid Thermal Annealing (RTA) was used to promote crystallization of BLT thin films. The thin films with RTA process were compared with those with non-RTA process on electrical properties. After RTA process, the remanent polarization value (2Pr) of BLT thin films annealed at 72$0^{\circ}C$ was 20.46 $\mu$C/$\textrm{cm}^2$ which was approximately 27% higher than that of non-RTA process at 5 V.

A Study on the Debinding Process of High Purity Alumina Ceramic Fabricated by DLP 3D Printing (DLP 3D 프린팅으로 제작된 고순도 알루미나 세라믹 탈지 공정 연구)

  • Lee, Hyun-Been;Lee, Hye-Ji;Kim, Kyung-Ho;Ryu, Sung-Soo;Han, Yoonsoo
    • Journal of Powder Materials
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    • v.27 no.6
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    • pp.490-497
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    • 2020
  • The 3D printing process provides a higher degree of freedom when designing ceramic parts than the conventional press forming process. However, the generation and growth of the microcracks induced during heat treatment is thought to be due to the occurrence of local tensile stress caused by the thermal decomposition of the binder inside the green body. In this study, an alumina columnar specimen, which is a representative ceramic material, is fabricated using the digital light process (DLP) 3D printing method. DTG analysis is performed to investigate the cause of the occurrence of microcracks by analyzing the debinding process in which microcracks are mainly generated. HDDA of epoxy acrylates, which is the main binder, rapidly debinded in the range of 200 to 500℃, and microcracks are observed because of real-time microscopic image observation. For mitigating the rapid debinding process of HDDA, other types of acrylates PETA, PUA, and MMA are added, and the effect of these additives on the debinding rate is investigated. By analyzing the DTG in the 25 to 300℃ region, it is confirmed that the PETA monomer and the PUA monomer can suppress the rapid decomposition rate of HDDA in this temperature range.

Coplanar Waveguides Fabricated on Oxidized Porous Silicon Air-Bridge for MMIC Application (다공질 실리콘 산화막 Air-Bridge 기판 위에 제작된 MMIC용 공면 전송선)

  • 박정용;이종현
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.5
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    • pp.285-289
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    • 2003
  • This paper proposes a 10 ${\mu}{\textrm}{m}$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and rnicrornachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation (50$0^{\circ}C$, 1 hr at $H_2O$/O$_2$) and rapid thermal oxidation (RTO) process (105$0^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to 10 ${\mu}{\textrm}{m}$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 1 dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about - 20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.