• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.950-958
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• 1988

We have implemented a RTA system using W-halogen lamps and tried to recrystallize the phosphorus ion implanted amorphous silicon on insultor (SOI) taking advantages of seeding window. The purpose of this study is to investigate the possibility of a typical crystalline orientation occurred during the solidifying process of molten amorphous silicon layer. Experimental results show that several twin boundaries are found on the seeding window region after annealing for 15 sec at 1040\ulcorner. These twin boundaries represent that the recrystallization is partialy possible and when the annealing is done at 1150\ulcorner, (100) etch pits with <110> facets are found on the solidified amorphous silicon layer. Consequently, Hall mobility of recrystallized silicon film is measured and the thermal behavior of grain boundary is also observed by SEM.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.46-55
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• 1998

This stud demonstrates the profiles of heavy ions (As, Sb) in silicon by high energy (1~10 MeV) implantation. Implanted profiles were measured by SIMS (Cameca 4f) and compared with simulation results (TRIM) program and analytical description method using Pearson function). The experimental results have a little bit deviation with simulation data in the case of As high energy implatation. But in the case of Sb, the experimental results are in good agreement with TRIM data. SIMS profiles are perfectly fitted with a analytical description method only using one pearson function in Sb implantation. but in the case of As, fitted profilesshow with a little bit deviations by channeling effects of SIMS profiles. Thermal annealing for electrical activation of implanted ions was carried out by furnace annealing and RTA(Rapid Thermal Annealing). Concentration-depth profile after heat treatement were measured by SR(Spreading Resistance) method.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1136-1139
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• 2009

Recently, various Ni doping systems and thermal annealing systems have been developed for fabrication of polycrystalline silicon film using SGS (super grain silicon) for medium and largesize AMOLED panels. In this study, we compare the potential of Ni doping systems including ALD (atomic layer deposition), AMD (atmospheric metal deposition), in-line sputter, and crystallization annealing systems including batch type furnace, inline furnace, and RTA (rapid thermal annealing) developed for the SGS method. Additional requirements for those systems to be used for mass production of large AMOLED TVs are suggested based on evaluation results for both poly-Si films and TFT backplanes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.329-332
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• 1999

In this paper, BST((Bao.&o,dTi0:3) thin films were deposited by the rf magnetron sputtering method on Pt/$SiO_2$/Si substrate. Pt, $RuO_2$, Ag, Cu films for the formation of top electrode were deposited on BST thm films. And then Top Electrodes/BST/Pt capacitors were annealed with rapid thermal annealing(RTA) at various temperature. We have investigated effect of post-annealing on the electrical properties such as dielectric constant and leakage current of the capacitors. It was found that electrical properties of the capacitors were greatly depended on the annealing temperatures as well as the materials of top electrodes. In BST thin films with Pt top electrode was annealed at $700^{\circ}C$. the dielectric constant was measured to the value of 346 at l[kHzl and the leakage current was obtained to the value of $8.76\times10^8$[A/$\textrm{cm}^2$] at the forward bias of 2[V].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.814-820
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• 1991

TaSi$_2$ was formed by rapid thermal annealing(RTA) on BF$_2$ doped single crystalline silicon substrates. The formation and various properties of TaSi$_2$ have been investigated by using 4-point probe, HP414, XRD, and SEM. And the redistribution of boron with RTA has been observed by SIMS. Implanted boron was diffused out into the TaSi$_2$ for RTA temperature but did not significantly affect the formation temperature of TaSi$_2$. Also, the contact resistance for TaSi$_2$/p$^{+}$ region had a low value 22$\Omega$, at contact size of 0.9$\mu$m, and the native oxide formed on Si-substrates by BF$_2$ implantation retarded the formation of TaSi$_2$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• Journal of the Korean institute of surface engineering
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• v.35 no.6
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Korean Journal of Materials Research
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• v.1 no.4
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• pp.191-197
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• 1991

The surface roughnesses of titanium silicide films and the diffusion behaviours of dopants in single crystal and polycrystalline silicon substrates durng titanium silicide formation by rapid thermal annealing(RTA) of sputter deposited Ti-filicide film from the composite $TiSi_{2.6}$ target were investigated by the secondary ion mass spectrometry(SIMS), a four-point probe, X-ray diffraction, and surface roughness measurements. The as-deposited films were amorphous but film prepared on single silicon substrate crystallized to the orthorhombic $TiSi_2$(C54 structure) upon rapid thermal annealing(RTA) at $800^{\circ}C$ for 20sec. There was no significant out-diffusion of dopants from both single crystal and polycrystalline silicon substrate into titanum silicide layers during annealing. Most of the implanted dopants piled up near the titanium silicide/silicon interface. The surface roughnesses of titanium silicide films were in the range between 16 and 22nm.