• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.190-197
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• 2010

The ACR (Access Control Router) of WiBro processes location registration of the Correspondent Node and Home Agent as the Correspondent Node moves between ACRs. Therefore, the location update cost is low compared with MIPv6. However, all packets which are sent and received are sent through the ACR, so as the number of mobile nodes that are managed by the ACR increases, the cost of packet delivery also increases. Therefore, the communication state of the ACR domain remains smooth when the ACR which manages the mobile node in the ACR domain has good performance. However, network delays occur unless the ACR performs well, so the role of the ACR is important. In this paper, we analysis performance of the ACR for efficient realization of the WiBro standard. By using the Deny Probability and the Total Profit of ACR performance and apply it to the Random Walk Mobility model as the mobility model.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.19-25
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• 2010

In this paper, the performance of the DoS information security algorithm is evaluated to provide the multimedia traffic between the nodes using the multicasting services. The essence technology for information security to distribute the multimedia contents is presented. Under the multicasting services, a node participating new group needs a new address and the node compares the collision with the existing nodes, then DoS attack can be occurred between the nodes by a malicious node. Using the NS2 simulator, the number of DoS attacks, the average number of trials to generate new address, and the average time to create address are analyzed. From simulation results, the efficient algorithm with relevant random number design according to the DRM network is needed to provide secure multimedia contents distribution.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.713-720
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• 2004

In this paper we suggest error control scheme to improve CLR performance degradation on wireless ATM access networks which consist of access node and wireless channel. Based on the cell scale and hurst scale, traffic model of wireless ATM access network is analyzed. The CLR equation due to buffer overflow for wireless access node is derived for VBR traffic. the CLR equation due to random bit errors and burst errors for wireless channel is derived. Using the CLR equation for both access node and wireless channel, the CLR equation of wireless ATM access network is derived, and we evaluate the CLR performance on the wireless ATM access networks with conventional SR ARQ scheme and recommended error control scheme, that is, Type I Hybrid ARQ scheme. It is confirmed that CLR performance of the access networks with recommended error control schemes is superior to that of access networks with conventional error control scheme.

• Journal of Astronomy and Space Sciences
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• v.29 no.3
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• pp.315-320
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• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.1
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• pp.45-50
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• 2014

A vibration test coupon is prepared with nine plastic ball grid array packages on a printed circuit board using SnPb solders, and a random vibration test is conducted on the coupon. Life data from the test are analyzed, and it is shown that over the board, life data is location-dependent. For investigating this location dependency, a finite element model is developed and the equivalent stresses, which are defined based on the stress response functions at each node, are investigated. It is shown that one of the corner solder balls has the maximum equivalent stress at a package during the test. Finally, it is demonstrated that the maximum equivalent stress and durability life are inversely proportional.

• Proceedings of the Korea Society for Simulation Conference
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• 1994.10a
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• pp.32-32
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• 1994

In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

• The KIPS Transactions:PartD
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• v.12D no.4 s.100
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• pp.543-552
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• 2005

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. The disk-based spatial indexing techniques, however, cannot direct apply to main memory databases, because the main purpose of disk-based techniques is to reduce the number of disk accesses. In main memory-based indexing techniques, the node access time is much faster than that in disk-based indexing techniques, because all index nodes reside in a main memory. Unlike disk-based index techniques, main memory-based spatial indexing techniques must reduce key comparing time as well as node access time. In this paper, we propose an efficient spatial index structure for main memory-based databases, called Tmr-tree. Tmr-tree integrates the characteristics of R-tree and T-tree. Therefore, Nodes of Tmr-tree consist of several entries for data objects, main memory pointers to left and right child, and three additional fields. First is a MBR of a self node, which tightly encloses all data MBRs (Minimum Bounding Rectangles) in a current node, and second and third are MBRs of left and right sub-tree, respectively. Because Tmr-tree needs not to visit all leaf nodes, in terms of search time, proposed Tmr-tree outperforms R-tree in our experiments. As node size is increased, search time is drastically decreased followed by a gradual increase. However, in terms of insertion time, the performance of Tmr-tree was slightly lower than R-tree.

• ETRI Journal
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• v.25 no.2
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• pp.140-143
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• 2003

In this paper, we present a probabilistic approach to determining whether extracted facial features from a video sequence are appropriate for creating a 3D face model. In our approach, the distance between two feature points selected from the MPEG-4 facial object is defined as a random variable for each node of a probability network. To avoid generating an unnatural or non-realistic 3D face model, automatically extracted 2D facial features from a video sequence are fed into the proposed probabilistic network before a corresponding 3D face model is built. Simulation results show that the proposed probabilistic network can be used as a quality control agent to verify the correctness of extracted facial features.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.460-462
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• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.160-160
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• 2003

This paper describes some of the key issues associated with the patterning of metal electrodes of sub-micron (especially at the critical dimension (CD) of 0.15 $\mu\textrm{m}$) dynamic random access memory (DRAM) devices. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 $\mu\textrm{m}$ and thus the storage node electrode with the CD of 0.15 $\mu\textrm{m}$ could not be fabricated using the Pt electrodes. Accordingly, we have proposed novel techniques to surmount the above difficulties. The Ru electrode for the stack-type structure is introduced and alternative schemes based on the introduction of the concave-type structure using Pt or Ru as an electrode material are outlined.