• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.12
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• pp.1675-1682
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• 2012

Weight reduction is increasingly being considered very important in light of air pollution and the exhaustion of resources. As a result, many automotive components are being replaced by Al and Mg alloys, and studies are increasingly focusing on the same. However, the use of Mg alloys is limited because they have higher material cost and lower productivity owing to the difficult forming conditions compared with Al alloys. In this study, the tube extrusion process conditions of an automotive bumper back beam were analyzed using FEA. Material tests were performed to determine the properties, and experiments and analyses for a simple shape were performed to define the data for heat generation during plastic deformation. Then, the analyses of the product were carried out by considering various temperatures and ram speeds. The conditions were then established, and a product without surface defects was extruded successfully.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1133-1138
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• 2018

Lightweight Encryption Algorithm (LEA) is one of the most promising lightweight block cipher algorithm due to its high efficiency and security level. There are many works on the efficient LEA implementation. However, many works missed the secure application services where the IoT platforms perform secure communications between heterogeneous IoT platforms. In order to establish the secure communication channel between them, the encryption should be performed in the on-the-fly method. In this paper, we present the LEA implementation performing the on-the-fly method over the ARM Cortex-M3 processors. The general purpose registers are fully utilized to retain the required variables for the key scheduling and encryption operations and the rotation operation is optimized away by using the barrel-shifter technique. Since the on-the-fly method does not store the round keys, the RAM requirements are minimized. The implementation is evaluated over the ARM Cortex-M3 processor and it only requires 34 cycles/byte.

• Journal of the Korean Society for Railway
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• v.11 no.4
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• pp.371-377
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• 2008

As a railway is receiving attention as an environment-friendly transportation mode, many high speed, inter-city and urban railway are constructed and remodeled in the world. With this trend, railway RAMS was included in the international standard IEC 62278 in 2002. RAMS activity in domestic market is also increased with this international trend. However, IEC 62278 does not describe the methodology of substantial contents like how reliability target is set although it can be used as an overall guideline when RAMS requirements are included in the purchase specification. That is because RAMS requirements should be set with the specific railway condition. It is required to fully understand the meaning of railway RAMS parameters and apply those correspond to the specific railway system and environment condition especially when a quantitative RAMS requirement is set. In this study, the meaning and characteristics of RAMS parameters applicable to the development of quantitative RAMS requirement of rolling stock is described. And the basic concept of RAMS and the definition of failure that IEC 62278 describes is modified and suggested in order to make more suitable to the development of quantitative RAMS requirement.

• The KIPS Transactions:PartB
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• v.17B no.3
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• pp.227-232
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• 2010

This paper proposes the real time lip reading method in the embedded environment. The embedded environment has the limited sources to use compared to existing PC environment, so it is hard to drive the lip reading system with existing PC environment in the embedded environment in real time. To solve the problem, this paper suggests detection methods of lip region, feature extraction of lips, and awareness methods of phonetic words suitable to the embedded environment. First, it detects the face region by using face color information to find out the accurate lip region and then detects the exact lip region by finding the position of both eyes from the detected face region and using the geometric relations. To detect strong features of lighting variables by the changing surroundings, histogram matching, lip folding, and RASTA filter were applied, and the properties extracted by using the principal component analysis(PCA) were used for recognition. The result of the test has shown the processing speed between 1.15 and 2.35 sec. according to vocalizations in the embedded environment of CPU 806Mhz, RAM 128MB specifications and obtained 77% of recognition as 139 among 180 words were recognized.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.417-424
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• 2019

This paper presents the design of a JPEG-LS codec for lossless image compression from AR/VR device. The proposed JPEG-LS(: LosSless) codec is mainly composed of a context modeling block, a context update block, a pixel prediction block, a prediction error coding block, a data packetizer block, and a memory block. All operations are organized in a fully pipelined architecture for real time image processing and the LOCO-I compression algorithm using improved 2D approach to compliant with the SBT coding. Compared with a similar study in JPEG-LS, the Block-RAM size of proposed STB-FLC architecture is reduced to 1/3 compact and the parallel design of the predication block could improved the processing speed.

• Journal of IKEEE
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• v.25 no.4
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• pp.634-643
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• 2021

In this paper, an FPGA-based acceleration scheme of range Doppler algorithm (RDA) is proposed for the real time synthetic aperture radar (SAR) imaging. Hardware architectures of matched filter based on systolic array architecture and a high speed sinc interpolator to compensate range cell migration (RCM) are presented. In addition, the proposed hardware was implemented and accelerated on Xilinx Alveo FPGA. Experimental results for 4096×4096-size SAR imaging showed that FPGA-based implementation achieves 2 times acceleration compared to GPU-based design. It was also confirmed the proposed design can be implemented with 60,247 CLB LUTs, 103,728 CLB registers, 20 block RAM tiles and 592 DPSs at the operating frequency of 312 MHz.

• The Journal of the Acoustical Society of Korea
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• v.25 no.6
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• pp.298-304
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• 2006

This paper proposes a ray-based forward modeling scheme which is suitable for the shallow water acoustic wave propagation simulations. The proposed model comprises of ray tracings for the layered media of which sound speed profiles are interpolated linearly. considerations of plane and spherical wave reflection coefficients. and calculations of the phases and the amplitudes of eigen rays. The main characteristic of the scheme is fast simulation time due to direct calculation of the broad-band time signals in the time-domain, i.e. without transformation of the frequency-domain solutions to the time si 밍 131s. Finally, we applied the model to 4-types of test environments and compared the resulting signals with those of ORCA and Ram in order to validate the proposed model.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2004.03a
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• pp.703-712
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• 2004

A variant of the magnetoplasma jet engine (magjet) is here proposed for airbreathing flight in the hypersonic regime. As shown in Figure 1, the engine consists of two distinct ducts: the high-speed duct, in which power is added electromagnetically to the incoming air by a momentum addition device, and the fuel cell duct in which the flow stagnation temperature is reduced by extracting energy through the use of a magnetoplas-madynamic (MPD) generator. The power generated is then used to accelerate the flow exiting the fuel cells with a fraction bypassed to the high-speed duct. The analysis is performed using a quasi one-dimensional model neglecting the Hall and ion slip effects, and fix-ing the fuel cell efficiency to 0.6. Results obtained show that the specific impulse of the magjet is at least equal to and up to 3 times the one of a turbojet, ram-jet, or scramjet in their respective flight Mach number range. Should the air stagnation temperature in the fuel cell compartment not exceed 5 times the incoming air static temperature, the maximal flight Mach number possible would vary between 6.5 and 15 for a magnitude of the ratio between the Joule heating and the work interaction in the MPD generator varied between 0.25 and 0.01, respectively. Increasing the mass flow rate ratio between the high speed and fuel cell ducts from 0.2 to 20 increases the engine efficiency by as much as 3 times in the lower supersonic range, while resulting in a less than 10% increase for a flight Mach number exceeding 8.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}