• Proceedings of the Korean Society for Technology of Plasticity Conference
• /
• 2005.05a
• /
• pp.266-269
• /
• 2005

The effect of exit temperature on the thickness of recrystallization layer during Al extrusion process was investigated. The recrystallization layer of an extruded Al alloy is an important feature of the product in a wide range of applications, particularly those within the automotive industry. The thicker recrystallized layer in the Al alloys can give rise to a number of problems including reduced fatigue resistance and orange peel during cold forming. But the interaction of extrusion process variables with the thickness of recrystallization layer is poorly understood, and there is limited information available regarding the role of the main hot extrusion variables. Using the 3650 US ton extrusion press, this paper describes the effect of the main process variables such as billet temperature, ram speed, and exit temperature on the thickness of recrystallization layer for the A6XXX Al alloy.

• Transactions of Materials Processing
• /
• v.3 no.3
• /
• pp.271-281
• /
• 1994

Titanium-6242 $({\alpha}+{\beta})$ alloy has been used for aircraft engine components such as disks and blades, because it has an excellent strength/weight ratio at high temperatures. When this material is forged to manufacture disks, process parameters should be carefully designed to control strain and temperature distributions within the process windows by which desirable mechanical properties can be produced. In the present investigation, it was intended to design the process parameters for a conventional hot forging of this material by using a rigid-thermoviscoplastic finite element analysis technique. It was assumed that the process was performed by a screw press which is capable of maintaining a constant ram speed during loading. From the analysis results, it was found out that the initial temperature of the workpiece and the die shape were important parameters to control the forging process. In result, these parameters were properly designed for hot forging of a disk with specific dimensions.

• Transactions of Materials Processing
• /
• v.27 no.6
• /
• pp.379-385
• /
• 2018

This study investigated the effect of extrusion conditions on microstructures and mechanical properties of AM80 magnesium alloys. The billets of magnesium alloy used for hot extrusion were prepared by permanent mold casting method, and its extrusion was hot direct extrusion with different extrusion conditions. The results of microstructural analysis showed that the main phases in the as-casted alloys were ${\alpha}-Mg$, ${\beta}-Mg_{17}Al_{12}$, and lamella $Mg_{17}Al_{12}$. Hot extrusion results, The tensile strength of the most soundly manufactured extruded bars (extrusion temp: $350^{\circ}C$, extrusion ratio: 27:1, ram speed: 2mm/s) was approximately 327MPa at room temperature. The increase in the mechanical properties of hot-extruded alloys was as a result of grain refinement by dynamical recrystallization during hot extrusion.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.1
• /
• pp.101-113
• /
• 1986

In this paper, a real-time pitch detector LPC vocoder as implemented on a high speed digital signal processor, NEC 7720, is described. The pitch detector was based mainly on the SIFT algorithm. The SIFT pitch detector consists primarily of a digital low pass filter, inverse filter, computation of autocorrelation, a peak picker, interpolation, V/UV defcision and a final pitch smoother. In our approach, modification, mainly on the V/UV decision and a final pitch smoother, was made to estimate more accurate pitches. An 16-bit fixed-point aithmatic was employed for all necessary computation and the simulated results were compared with the eye detected pitches obtained from real speech data. The pitch detector occupies 98.8% of the instruction ROM, 37% of the data ROM, and 94% of internal RAM and takes 15.2ms to estimate a pitch when an analysis frame is consisted of 128 sampled speech data. It is observed that the tested results were well agreed with the computer simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.10
• /
• pp.57-64
• /
• 2002

The structure of conventional CAM(Content Addressable Memory) cell, used to Look-up table scheme in Huffman CODEC, is not performed by being separated in reading, writing and match operation. So, there is disadvantages that the control is complicated, and the floating states of match line force wrong operation to be happened in reading, writing operation. In this paper, in order to improve the disadvantages and proces the data fast, fast Look-up table is designed using DBLCAM(Dual Bit Line CAM)-performing the reading, writing operation and match operation independently and Two-port SRAM being more fast than RAM in an access speed. Look-up table scheme in Huffman CODEC, using DBLCAM and Two-port SRAM proposed in this paper, is designed in Cadence tool, and layout is performed in 0.6${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS full custom. And simulation is peformed with Hspice.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.4 s.334
• /
• pp.29-36
• /
• 2005

This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.

• Journal of the Korean earth science society
• /
• v.24 no.6
• /
• pp.533-548
• /
• 2003

The prevailing wind phenomenon around Pohang in winter was investigated by using surface and vertical observatory datas and a numerical simulation was carried out to analyse this phenomenon using RAMS. Direction of the prevailing wind was westerly at upper atmosphere. However, near the surface, southwestern wind prevailed in winter. Using the RAMS to simulate a winter wind system numerically, it was found out that this phenomenon was strongly affected by the geographical features such as directions of coastline and low level valley, and distributions of land and sea. To investigate the accuracy of the model results, wind speed, temperature and wind direction of typical continuous southwestern wind occurring days were compared with observation data. Analyzing the characteristics of local circulation system was very hard because of horizontally sparse observation data. But from the result above, a numerical simulation using the RAMS, which satisfies the spatial high resolution, will provide more accurate results.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.1
• /
• pp.46-56
• /
• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4A
• /
• pp.473-478
• /
• 2008

WAVE is a short-to-medium range communication standard that supports both public safety and private operations in roadside-to-vehicle and vehicle-to-vehicle communication environments. The core technology of physical layer in WAVE is orthogonal frequency division multiplexing (OFDM), which is sensitive to timing synchronization error. Besides, minimizing the latency in communication link is an essential characteristic of WAVE system. In this paper, a robust, low-complexity and small-latency timing synchronization algorithm suitable for WAVE system and its efficient hardware architecture are proposed. The comparison between proposed algorithm and other algorithms in terms of computational complexity and latency has shown the advantage of the proposed algorithm. The proposed architecture does not require RAM (Random Access Memory) which can affect the pipe lining ability and high speed operation of the hardware implementation. Synchronization error rate (SER) evaluation using both Matlab and FPGA implementation shows that the proposed algorithm exhibits a good performance over the existing algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.11
• /
• pp.1-11
• /
• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.