• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.144-152
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• 1996

In this paper, a pulse-mode digital multilayer neural network with a massively parallel yet compact and flexible network architecture is presented. Algebraicneural operations are replaced by stochastic processes using pseudo-random pulse sequences and simple logic gates are used as basic computing elements. The distributions of the results from the stochastic processes are approximated using the hypergeometric distribution. A statistical model of the noise(error) is developed to estimate the relative accuracy associated with stochastic computing in terms of mean and variance. Numerical character recognition problems are applied to the network to evaluate the network performance and to justify the validity of analytic results based on the developed statistical model. The network architectures are modeled in VHDL using the mixed descriptions of gate-level and register transfer level (RTL). Experiments show that the statistical model successfully predicts the accuracy of the operations performed in the network and that the character classification rate of the network is competitive to that of ordinary Back-Propagation networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.1
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• pp.97-108
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• 2013

Recently, mobile devices were increased and there was a sharp rise in demand. To exploit the location information of each device, many researcher was studying locating systems. The favorite locating or positioning systems were a GPS using satellites and a RTLS using wireless communication between devices. If some obstacle existed nearby the target device, The system have difference of performance. The obstacles near targets were caused signal disconnection and reflection because of NLOS condition. As the result, the NLOS condition degrade the locating performance. In this paper, we propose a locating system which is cooperated two systems using information reliability estimates from LOS/NLOS condition. We developed proposed system. In addition, we performed fields test and simulation tests at various environment for performance evaluation. As the result, the test showed 97% success rate to estimate NLOS condition. Furthermore, the simulation result of our locating system was increased to 89% compared with a single system.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.