• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.1009-1015
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• 2014

Chalcopyrite $CuInSe_2$ (CIS) thin films were prepared without Se- / S-containing gas by co-sputtering using $CuSe_2$ and $InSe_2$ selenide-targets and rapid thermal annealing. The grain size increased to a maximum of 54.68 nm with a predominant (112) plane. The tetragonal distortion parameter ${\eta}$ decreased and the inter-planar spacing $d_{(112)}$ increased in the RTA-treated CIS thin films annealed at a $400^{\circ}C$, which indicates better crystal quality. The increased carrier concentration of RTA-treated p-type CIS thin films led to a decrease in resistivity due to an increase in Cu composition at annealing temperatures ${\geq}350^{\circ}C$. The optical band gap energy ($E_g$) of CIS thin films decreased to 1.127 eV in RTA-treated CIS thin films annealed at $400^{\circ}C$ due to the improved crystallinity, elevated carrier concentration and decreased In composition.

• Korean Journal of Materials Research
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• v.26 no.6
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• pp.347-352
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• 2016

ZnO with wurtzite structure has a wide band gap of 3.37 eV. Because ZnO has a direct band gap and a large exciton binding energy, it has higher optical efficiency and thermal stability than the GaN material of blue light emitting devices. To fabricate ZnO devices with optical and thermal advantages, n-type and p-type doping are needed. Many research groups have devoted themselves to fabricating stable p-type ZnO. In this study, $As^+$ ion was implanted using an ion implanter to fabricate p-type ZnO. After the ion implant, rapid thermal annealing (RTA) was conducted to activate the arsenic dopants. First, the structural and optical properties of the ZnO thin films were investigated for as-grown, as-implanted, and annealed ZnO using FE-SEM, XRD, and PL, respectively. Then, the structural, optical, and electrical properties of the ZnO thin films, depending on the As ion dose variation and the RTA temperatures, were analyzed using the same methods. In our experiment, p-type ZnO thin films with a hole concentration of $1.263{\times}10^{18}cm^{-3}$ were obtained when the dose of $5{\times}10^{14}$ As $ions/cm^2$ was implanted and the RTA was conducted at $850^{\circ}C$ for 1 min.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.387-390
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• 1988

The increases in the packing density and the resulting shrinkage of silicon integrated circuit dimensions led to the investigation and successful of the deposited silicide layers as the gate and interconnection and contact metallization. In this paper evaporated Co films on n-Si have been rapid thermal annealed in $N_2$ambient at temperature of $400^{\circ}C-1000^{\circ}C$. The Co silicide formation is characterized by sheet resistance (4PP). Also, silicide growth rate and its reproductivity has been examined by SEM.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1137-1139
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• 1993

The superconducting thin films of $YBa_2Cu_3O_{7-x}$ were deposited on (100) sapphire substrates at low temperature by rf magnetron sputtering and annealed at $895^{\circ}C$ for 60 sec. using rapid-thermal-annealing(RTA) technique. The films were characterized by SEM, four-point probe resistivity measurement, XRD, and AES. The RTA processed HTS films had a preferential structure with c-axis normal to the substrate surface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.266-272
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• 2009

In the present work three dimensional process and device simulations were employed to study the performance variations with RTA. It is observed that with the increase in RTA temperature, the arsenic dopants from the source /drain region diffuse laterally under the spacer region and simultaneously acceptors (Boron) are redistributed from the central axis region of the fin towards the Si/SiO2 interface. As a consequence both drive current and peak cut-off frequency of an n-FinFET are observed to improve with RTA temperatures. Volume inversion and hence the flow of carries through the central axis region of the fin due to reduced scattering was found behind the performance improvements with increasing RTA temperature.

• Korean Journal of Materials Research
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• v.24 no.9
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• pp.443-450
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• 2014

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.4
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• pp.184-189
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• 2002

The electrical and optical properties of $(Pb_{0.91}La_{0.09})(Zr_{0.65}Ti_{0.35})O_3$(PLZT) thin films by MOCVD using ultrasonic spraying were investigated. To compensate the Pb loss by evaporation, 5 and 10 wt% of excess Pb was added to 0.2 M precursor. After deposition of films on ITO-coated glasses in oxygen atmosphere for 30 min, films were heated by in-situ RTA (rapid thermal annealing) method. When the films were heat treated at $600^{\circ}C$, perovskite single phase was obtained. The optical property of the film with 10 wt% excess Pb was excellent showing about 84 % of transmittance near 520 nm. The dielectric constant of the film was about 308 and the leakage current of the film was lower than the Pb excess 0, 5 wt% PLZT thin films.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.2
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• pp.106-110
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• 1998

The $LiNbO_3$ thin films were prepared directly on Si(100) substrates by conventional RF magnetron spurttering system for nonvolatile memory applications. RTA(Rapid Thermal Annealing) treatment was performed for as-deposited films in an oxygen atmosphere at 600 $^{\circ}C$ for 60 s. The rapid thermal annealed films were changed to poly-crystalline ferroelectric nature from amorphous of as-deposition. The resistivity of the ferroelectric $LiNbO_3$ film was increased from a typical value of $1{\sim}2{\times}10^8{\Omega}{\cdot}cm$ before the annealing to about $1{\times}10^{13}{\Omega}{\cdot}cm$ at 500 kV/cm and reduced the interface state density of the $LiNbO_3/Si$ (100) interface to about $1{\times}10^{11}/cm^2{\cdot}eV$. Ferroelectric hysteresis measurements using a Sawyer-Tower circuit yielded remanent polarization ($P_r$) and coercive field ($E_c$) values of about 1.2 ${\mu}C/cm^2$ and 120 kV/cm, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.186-186
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• 2010

소자의 축소화에 따라 floating gate 형의 flash 메모리 소자는 얇은 게이트 절연막 등의 이유로, 이웃 셀 간의 커플링 및 게이트 누설 전류와 같은 문제점을 지니고 있다. 이러한 문제점을 극복하기 위해 charge trap flash 메모리 (CTF) 소자가 연구되고 있지만, CTF 메모리 소자는 쓰기/지우기 속도와 데이터 보존 성능간의 trade-off 관계와 같은 문제점을 지니고 있다. 최근, 이를 극복하기 위한 방안으로, 다른 유전율을 갖는 유전체들을 적층시킨 터널 절연막을 이용한 Tunnel Barrier Engineered (TBE) 기술이 주목 받고 있다. 따라서, 본 논문에서는 TBE 기술을 적용한 MIS-capacitor를 높은 유전율을 가지는 Al2O3와 HfO2를 이용하여 제작하였다. 이를 위해 먼저 Si 기판 위에 Al2O3 /HfO2 /Al2O3 (AHA)를 Atomic Layer Deposition (ALD) 방법으로 약 2/1/3 nm의 두께를 가지도록 증착 하였고, Aluminum을 150 nm 증착 하여 게이트 전극으로 이용하였다. Capacitance-Voltage와 Current-Voltage 특성을 측정, 분석함으로써, AHA 구조를 가지는 터널 절연막의 전기적인 특성을 확인 하였다. 또한, high-k 물질을 이용한 터널 절연막을 급속 열처리 공정 (Rapid Thermal Annealing-RTA) 과 H2/N2분위기에서 후속열처리 공정 (Post-RTA)을 통하여 전기적인 특성을 개선 시켰다. 적층된 터널 절연막은 열처리를 통해 터널링 전류의 민감도의 향상과 함께 누설전류가 감소됨으로서 우수한 전기적인 특성이 나타남을 확인하였으며, 적층된 터널 절연막 구조와 적절한 열처리를 이용하여 빠른 쓰기/지우기 속도와 전기적인 특성이 향상된 비휘발성 메모리 소자를 기대할 수 있다.

• Korean Journal of Materials Research
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• v.11 no.9
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• pp.776-780
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• 2001

$SiO_2$ and polycrystalline Si layers were sequentially grown on (100) Si. NiSi was formed on this substrate from a 20nm Ni layer or a 20nm Ni/5nm Ti bilayer by rapid thermal annealing (RTA) at $300~500^{\circ}C$ to compare thermal stability. In addition, MOS capacitors were fabricated by depositing a 20nm Ni layer on the Poly-Si/$SiO_2$substrate, RTA at $400^{\circ}C$ to form NiSi, $BF_2$ or As implantation and finally drive- in annealing at $500~800^{\circ}C$ to evaluate electrical characteristics. When annealed at $400^{\circ}C$, NiSi made from both a Ni monolayer and a Ni/Ti bilayer showed excellent thermal stability. But NiSi made from a Ni/Ti bilayer was thermally unstable at $500^{\circ}C$. This was attributed to the formation of insignificantly small amount of NiSi due to suppressed Ni diffusion through the Ti layer. PMOS and NMOS capacitors made by using a Ni monolayer and the SADS(silicide as a dopant source) method showed good C-V characteristics, when drive-in annealed at $500^{\circ}C$ for 20sec., and$ 600^{\circ}C$ for 80sec. respectively.