• Journal of Magnetics
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• 제6권4호
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• pp.126-128
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• 2001

The effect of rapid thermal anneal (RTA) has been investigated on the properties of an FeMn exchange-biased magnetic tunnel junction (MTJ) using magnetoresistance and I-V measurements and transmission electron microscopy (TEM). The tunneling magnetoresistance (TMR) in an as-grown MTJ is found to be ∼27%, while the TMR in MTJs annealed by RTA increases with annealing temperature up to 300$\^{C}$, reaching ∼46%. A TEM image reveals a structural change in the interface of A1$_2$O$_3$layer for the MTJ annealed by RTA at 300$\^{C}$. The oxide barrier parameters are found to vary abruptly with annealing time within a few ten seconds. Our results demonstrate that the present RTA enhances the magnetoresistive properties of MTJs.

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.37-42
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• 2004

본 논문에서는 선비정질화, 저에너지 이온 주입, 이중 열처리 공정을 이용하여 p/sup ＋/-n 박막 접합을 형성하였다. Ge 이온을 이용하여 결정 Si 기판을 선비정질화하였다. 선비정질화된 시편과 결정 기판에 p-형 불순물인 BF₂이온을 주입하여 접합을 형성하였다. 열처리는 급속 열처리 (RTA : rapid thermal anneal) 방법과 850℃의 노 열처리 (FA : furnace anneal) 방법을 병행하였다. 두 단계의 이중 열처리 방법으로 네 가지 조건을 사용하였는데, 이는 RTA(750℃/10초)＋Ft, FA＋RTA(750℃/10초), RTA(1000℃/10초)＋F4 FA＋RTA(1000℃/10초)이다. Ge 선비정질화를 통하여 시편의 접합 깊이를 감소시킬 수 있었다. RTA 온도가 1000℃인 경우에는 RTA보다는 FA를 먼저 수행하는 것이 접합 깊이(x/sub j/), 면저항(R/sub s/), R/sub s/ x/sub j/, 누설 전류 등의 모든 면에서 유리함을 알 수 있었다.

• 한국재료학회지
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• 제12권10호
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.500-501
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• 2005

Aluminum doped zinc oxide films (ZnO:Al) were deposited on glass substrate by DC magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The effects of substrate bias on the electrical properties and film structure were studied. Films deposited with positive bias have been annealed at $600^{\circ}C$ using rapid thermal anneal (RTA) process. The effects of RTA on the evolution of film microstructure are to be also studied using X-ray diffraction, transmission electron microscopy, and atomic force microscopy. Positive bias sputtering may induce lattice defects caused by electron bombardments during deposition. The as-deposited film microstructure evolves from the film with high defect density to more stable film condition. The electrical properties of the films after RTA process were also studied and the results were correlated with the evolution of film microstructures.

• 대한전자공학회논문지TE
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• 제39권1호
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• pp.31-36
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• 2002

낮은 에너지의 보론 이온을 선비정질화된 실리콘 기판과 단결정 기판에 이온 주입하여 0.2μm 정도의 접합 깊이를 갖는 박막의 P/sup +/-n 접합을 형성하였다 이온주입에 의한 결정결함의 제거 및 주입된 보론 이온의 활성화를 위해 급속 열처리기를 이용하였으며, BPSC(bore-phosphosilicate glass)를 흐르도록 하기 위해 노 열처리를 도입하였다. 선비정질화 이온주입은 45keV, 3×10/sup 14/cm/sup -2/ Ge 이온을 사용하였으며, p형 불순물로는 BF2 이온을 20keV, 2×10/sup 15/cm /sup -2/로 이온주입 하였다. 급속 열처리와 노 열처리 조건은 각각 1000。C/ 10초와 850。C/4O분이었다. 형성된 접합의 접합깊이는 SIMS와 ASR로 측정하였으며, 4-point probe로 면 저항을 측정하였다. 또한 전기적인 특성은 다이오드에 역방향 전압을 인가하여 측정된 누설전류로 분석하였다. 측정 결과를 살펴보면, 급속 열처리만을 수행하여도 양호한 접합 특성을 나타내나, 급속 열처리와 노 열처리를 함께 고려해야 할 경우에는 노 열처리 후에 급속 열처리를 수행하는 공정이 급속 열처리 후에 노 열처리를 수행하는 경우보다 더 우수한 박막 접합 특성을 나타내었다.

• 한국전기전자재료학회논문지
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• 제22권12호
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• pp.1095-1099
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• 2009

As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.

• 한국진공학회지
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• 제17권2호
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• pp.156-159
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• 2008

Pseudo-MOSFET 방법을 이용하여 Ge농도에 따른 SiGe-on-Insulator(SGOI) 기판의 특성을 평가하였다. SGOI 기판은 compressive-SiGe / Relaxed-Si / Buried oxide / Si-substrate 구조로 SOI 기판 위에 에피택셜 성장법으로 SiGe층을 형성하였으며 compressive SiGe층의 Ge 농도는 각각 16.2％, 29.7％, 34.3％, 56.5％ 이다. 실험결과 Ge 농도가 증가함에 따라 누설전류가 증가하는 특성을 보였으며 threshold voltage는 nMOSFET의 경우 3V에서 7V로 이동하였으며 pMOSFET의 경우도 -7 V에서 -6 V로 이동하는 특성을 보였다. 급속 열처리 공정 (rapid thermal anneal) 후에 매몰 산화층과 기판 계면간의 스트레스에 의한 포획준위가 발생하여 소자특성이 열화되었지만, $H_2/N_2$ 분위기에서 후속 열처리 공정 (post RTA anneal) 을 통하여 계면 간의 포획준위를 감소시켜 SGOI Pseudo-MOSFET의 전기적 특성이 개선되었다.

• Journal of the Optical Society of Korea
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• 제20권1호
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• pp.130-134
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• 2016

The influence of Au/Ni-based contact formed on a lightly-doped (7.3×1017cm−3, Zn-doped) InGaAsP layer for electrical compensation of surface plasmon polariton (SPP) propagation under various rapid thermal annealing (RTA) conditions has been studied. The active control of SPP propagation is realized by electrically pumping the InGaAsP multiple quantum wells (MQWs) beneath the metal planar waveguide. The metal planar film acts as the electric contact layer and SPP waveguide, simultaneously. The RTA process can lower the metal-semiconductor electric contact resistance. Nevertheless, it inevitably increases the contact interface morphological roughness, which is detrimental to SPP propagation. Based on this dilemma, in this work we focus on studying the influence of RTA conditions on electrical control of SPPs. The experimental results indicate that there is obvious degradation of electrical pumping compensation for SPP propagation loss in the devices annealed at 400℃ compared to those with no annealing treatment. With increasing annealing duration time, more significant degradation of the active performance is observed even under sufficient current injection. When the annealing temperature is set at 400℃ and the duration time approaches 60s, the SPP propagation is nearly no longer supported as the waveguide surface morphology is severely changed. It seems that eutectic mixture stemming from the RTA process significantly increases the metal film roughness and interferes with the SPP signal propagation.

• 전자공학회논문지A
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• 제31A권9호
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• pp.78-88
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• 1994

The electrical properties of TiM/TiSi$_{2}$ bilayer formed by rapid thermal anneal in NH$_{3}$ ambient after the Ti film is deposited on silicon cubstrate are investigated. N$^{+}$ contact resistance slightly increases with increasing annealing temperature with P$^{+}$ contact resistance decreases. The contact resistance of N$^{+}$ contance was less than 24[.OMEGA.] but P$^{+}$ thatn that of N$^{+}$ contact but the leakage current indicates degradation of the contact at high annealing temperature for both N$^{+}$ and contacts. The leakage current of N$^{+}$ Junction was less than 0.06[fA/${\mu}m^{2}$] but P$^{+}$ contact was 0.11-0.15[fA/${\mu}m^{2}$]. The junction breakdown voltage for N$^{+}$ junction remains contant with increasing annealing temperature while P$^{+}$ junction slightly decreases. The Electrical properties of a two step annealing are better than that of one step annealing. The Tin/TiSi$_{2}$ bilayer formed by RTA in NH$_{3}$ ambient reveals good electrical properties to be applicable at ULSI contact.

• 대한전기학회논문지
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• 제41권6호
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• pp.633-639
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• 1992

The physical and electrical properties of TiN/TiSiS12T contact barrier were studied. The TiN/TiSiS12T system was formed by rapid thermal anneal in NS12T ambient after the Ti film was deposited on silicon substrate. The Ti film reacts with NS12T gas to make a TiN layer at the surface and reacts with silicon to make a TiSiS12T layer at the interface respectively. It was found that the formation of TiN/TiSiS12T system depends on RTA temperature. In this experiment, competitive reaction for TiN/TiSiS12T system occured above $600^{\circ}C$. Ti-rich TiNS1xT layer and Ti-rich TiSiS1xT layer were formed at $600^{\circ}C$. stable structure TiN layer and TiSiS1xT layer which has CS149T phase and CS154T phase were formed at $700^{\circ}C$. Both stable TiN layer and CS154T phase TiSiS12T layer were formed at 80$0^{\circ}C$. The thickness of TiN/TiSiS12T system was increased as the thickness of deposited Ti film increased.