• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.787-792
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• 2004

This paper shows the design, fabrication and performance of oscillator appled to 5.5GHz RF module for local wireless communication system. Super low noise HJ FET of NE3210S01 is used to obtain a good phase noise Performance. The design Parameters for the optimum operating performance are simulated with ADS simulation. The measured out Power is 10 dBm at 5.5GHz, the second harmonic suppression -31 dBc, and the phase noise characteristics -98.83 dBc at 100kHz offset frequency, respectively. This implemented oscillator is available to local wireless Communication system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.96-100
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• 2004

This paper shows the design, fabrication and performance of oscillator appled to 5.5GHz RF module for local wireless communication system. Super low noise HJ FET of NE3210S01 is used to obtain a good phase noise Performance. The design Parameters for the optimum operating performance are simulated with ADS simulation. The measured out Power is 10 ㏈m at 5.5GHz, the second harmonic suppression -31 ㏈c, and the phase noise characteristics -98.83 ㏈c at 100KHz offset frequency, respectively. This implemented oscillator is available to local wireless Communication system.

• Journal of the Korea Society of Computer and Information
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• v.10 no.1 s.33
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• pp.175-180
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• 2005

Transmission speed becomes high speedization gradually in system while is the latest microwave and millimeter wave communication and user's demand is trend that also increase rapidly. To accommodate wider band width therefore, signalman who have high frequency and not required welsh suppression special quality little more is required. Designed oscillator, point Parts, in duplex all communication systems several systems studies that can keep pace with a lot of amount of informations in modern info-age are archieved vigrously.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.1
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• pp.98-107
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• 1998

For implementation of FM-DS/SS system. This paper has analyzed SO(Synchronous Oscillator) being oscillated by the motivation of injected signal. Transmitter has adopted FM-DS/SS modulation method using RF output-signal of FM. Receiver is used SO to demodulation of FM-DS/SS and applied sliding correlator for synchronization of PN clock. As a result of the inspection, SO presented stable lock ability in spite of doppler apperance and proved the synchronous properties of it in the FM-DS/SS system.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.11
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• pp.536-543
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• 2003

In this paper, we describe a unique self oscillating and mixing (SOM) down-converter design using a modified defected ground structure (DGS). The proposed SOM converter is consisted of self-oscillator, which can produce negative resistance and select resonance frequency, RF matching circuit, and IF low pass filter. As the advantage of this SOM converter can mix LO and RF signals as well as inducing LO signal with only one active device. it is designed as a simple structure and the low cost. Also, there is easy advantage to be applied in RFIC/MMIC technology because it offers excellent phase noise performance in spite of using micro-strip structure. The LO signal for the proposed SOM converter is designed at 1㎓ and RF frequency was chosen to be 800MHz. The achieved conversion loss and phase noise performances of the implemented SOM converter are 15㏈ and -95dBc/Hz at 100KHz offset frequency respectively. The equivalent circuit parameters for DGS are extracted by using a three dimensional EM simulator and simple circuit analysis method.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.964-970
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• 2013

This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 ${\mu}m$ consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 $mm^2$ and 0.029 $mm^2$, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2286-2292
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• 2011

In this paper we present the design of Low Noise Amplifier(LNA), mixer and filter for RF front-end part of partial discharge monitoring system. The monitoring system of partial discharge in high voltage power machinery is used to prevent many kinds of industrial accidents, and is usually composed of three parts - sensor, RF front-end and digital microcontroller unit. In our study, LNA, mixer and filter are key components of the RF front-end. The LNA consists of common gate and common source-cascaded structure and uses the resistive feedback for broad band matching. A coupled line structure is utilized to implement the filter, of which size is reduced by the meander structure. The mixer is designed using dual gate structure for high isolation between RF and local oscillator signal.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.118-125
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• 2003

This paper presents a 5.8-㎓ oscillator that uses a novel defected ground structure(DGS), which is etched on the metallic ground plane. As the suggested defected ground structure is the structure for mounting an active device, it is the roles of a feedback loop inducing a negative resistance as well as a frequency-selective circuit. Applying the feedback loop between the drain and the gate of a FET device produces precise phase conversion in the feedback loop. The equivalent circuit parameters of the DGS are extracted by using a three-dimensional EM simulation ,md simple circuit analysis method. In order to demonstrate a new DGS oscillator, we designed the oscillator at 5.8-㎓. The experimental results show 4.17 ㏈m output power with over 22 % dc-to-RF power efficiency and - 85.8 ㏈c/Hz phase noise at 100 KHz offset from the fundamental carrier at 5.81 ㎓.

• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.122-131
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• 2008

In this paper, an S-band oscillator of the low phase noise property using miniaturized microstrip hairpin shaped ring resonator has been designed and implemented. The TACONIC's RF-35 substrate has a dielectric constant ${\varepsilon}_r$=3.5 a thickness h=20mil a copper thickness t=17 um and loss tangent $tan{\delta}$=0.0025. The designed and implemented 2.45 GHz oscillator shows low phase performance of -100.5 dBc/Hz a 100kHz offset. Output power 20.9 dBm at center frequency 2.45 GHz and harmonic suppression -32 dBc. The circuit was implemented with hybrid technique. But can be fully compatible with the RFIC's, MIC and MMIC due to its entirely planar structure.