• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.875-880
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• 2019

A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.14 no.4
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• pp.123-134
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• 2004

In this paper a high speed architecture of the RC4 stream cipher is proposed and its FPGA implementation is presented. Compared to the conventional RC4 designs which have long initialization operation or use double or triple S-arrays to reduce latency delay due to S-array initialization phase, the proposed architecture for RC4 stream cipher eliminates the S-array initialization operation using 256-bit valid entry scheme and supports 40/128-bit key lengths with efficient modular arithmetic hardware. The proposed RC4 stream cipher is implemented using Xilinx XCV1000E-6H240C FPGA device. The designed RC4 stream cipher has about a throughput of 106 Mbits/sec at 40 MHz clock and thus can be applicable to WEP processor and RC4 key search processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.13-23
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• 2001

This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.282-290
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• 2003

AMR(Automatic Meter Reading) and RC(Remote Control) System have been researched from former several decade for a various power rate system, a efficient power service and rising of personal expenses, etc. But the existing AMR and RC System have disadvantage which are complex and high cost to install an individual communication network of electricity company. This paper proposed a new type of AMR and RC System using PLC with Web. and made components for proposal system. Most customer who live in apartment have an internet cable in the Republic of Korea. Therefore there is no more installation component for communication in proposal system at the apartment, except Web server system and PLC modem. so we made the PLC modem the digital watt-hour meter with a build in PLC modem and the software on server computer for establishing the proposal system.

• Annual Conference of KIPS
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.1
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• pp.96-103
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• 2009

This paper presents a L3 mobile terminal platform of the mobile terminal system which is a subsystem of HMm(Hig-speed Mobile Multimedia) system, which layer 3 control protocols such as RC(Radio Control), SC(Session Control), MC(Mobility Control) and application services such as VOD, FTP, VoIP for a multimedia mobile terminal are implemented on. The hardware platform is based on PXA255 and supports various interfaces and multimedia devices, and under the platform, an embedded Linux generated by the self-maden cross-toolchain, L3 control protocols and application programs were installed. The operation of HMm system under the HMm testbed has shown that this platform successfully supported SIP services, web browsing services, streaming services and etc as well as call processing. It could be the reference of the upcoming Fourth-Generation mobile terminal which the multimedia functionality will be enforced.

• Proceedings of the Korean Society of Computational and Applied Mathematics Conference
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• 2003.09a
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• pp.2.1-2
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• 2003

WLAN의 매체 특성상 AP beacon영역 내의 모든 STA들은 다른 STA의 송수신 데이터 내용에 접근할 수 있다. 따라서 상호 또는 그룹 간의 데이터프라이버시와 상호인증 서비스는 무선 랜의 중요한 이슈중의 하나이다. 무선랜을 통한 네트워크 접속 보안으로는 사용자와 AP 사이의 무선 접속구간 보안과 AP와 AS사이의 유선 구간 보안으로 정의되며, 상대적으로 취약한 무선 구간 보안이 초점이 된다. 현재 무선 구간 보안에는 WEP이 사용된다. 그러나 WEP 방식은 WEP 키와 IV 크기가 작고, 노출된 공유키를 사용하며, 암호 알고리즘(RC4)와 무결성 알고리즘(CRC-32)이 근본적으로 취약하다. 이러한 문제에 대한 해결 방법으로 IEEE 802.11i는 두 가지 접근 방식을 채택하였다. 하나는 WEP의 보안 문제점을 소프트웨어적으로 개선한 TKIP이고 다른 하나는 기존의 WEP과는 하드웨어적으로 상이한 AES을 기반으로 한 CCMP이다. 이 논문에서는 각 알고리즘에 대한 키의 흐름 및 그 안전성을 분석하였다. 이러한 방법을 통해 WEP 구조의 보안상의 취약점을 확인하고, TKIP이 WEP을 대체할 수 있을 만큼의 안전성을 갖는지를 검증한다. 또한 고려될 수 있는 공격 모델을 제시하고, 이에 대하여 알고리즘에 부가적으로 요구되는 보완점에 대해 논한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.3
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• pp.23-32
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• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8A
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• pp.640-647
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• 2009

IEEE 802.11i is an amendment to the original IEEE 802.11/b,a,g standard specifying security mechanism by stipulating RSNA for tighter security. The RSNA uses TKIP(Temporal Key Integrity Protocol) and CCMP(Counter with CBC-MAC Protocol) instead of old-fashioned WEP(Wired Equivalent Privacy) for data encryption. This paper describes a design of a communication security engine for IEEE 802.11i MAC layer. The design includes WEP and TKIP modules based on the RC4 encryption algorithm, and CCMP module based on the AES encryption algorism. The WEP module suffices for compatibility with the IEEE 802.11 b,a,g MAC layer. The CCMP module has about 816.7Mbps throughput at 134MHz, hence it satisfies maximum 600Mbps data rate described in the IEEE 802.11n specifications. We propose a pipelined AES-CCMP cipher core architecture, which has lower hardware cost than existing AES cores, because CBC mode and CTR mode operate at the same time.