• Title/Summary/Keyword: RAM-D

Search Result 323, Processing Time 0.03 seconds

Integration Process and Reliability for $SrBi_2$ $Ta_2O_9$-based Ferroelectric Memories

  • Yang, B.;Lee, S.S.;Kang, Y.M.;Noh, K.H.;Hong, S.K.;Oh, S.H.;Kang, E.Y.;Lee, S.W.;Kim, J.G.;Shu, C.W.;Seong, J.W.;Lee, C.G.;Kang, N.S.;Park, Y.J.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.1 no.3
    • /
    • pp.141-157
    • /
    • 2001
  • Highly reliable packaged 64kbit ferroelectric memories with $0.8{\;}\mu\textrm{m}$ CMOS ensuring ten-year retention and imprint at 125^{\circ}C$ have been successfully developed. These superior reliabilities have resulted from steady integration schemes free from the degradation, due to layer stress and attacks of process impurities. The resent results of research and development for ferroelectric memories at Hynix Semiconductor Inc. are summarized in this invited paper.

  • PDF

Allocation Model of RAM-B Design Goal for Vehicle System (기동장비 RAM-D 설계목표 할당 모델)

  • 한상철;김대용
    • Proceedings of the Korean Reliability Society Conference
    • /
    • 2001.06a
    • /
    • pp.513-520
    • /
    • 2001
  • 신규개발장비에 대하여 사용자가 제시한 RAM-D 요구조건을 만족하기 위한 하부 체계의 RAM-D 설계목표 설정 절차 및 방법에 대하여 기동무기체계의 대표적 장비인 전차를 대상으로 연구하여 RAM-D 요소별 할당 모델을 개발하였다.

  • PDF

FeRAM Technology for System on a Chip

  • Kang, Hee-Bok;Jeong, Dong-Yun;Lom, Jae-Hyoung;Oh, Sang-Hyun;Lee, Seaung-Suk;Hong, Suk-Kyoung;Kim, Sung-Sik;Park, Young-Jin;Chung, Jin-Young
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.2 no.2
    • /
    • pp.111-124
    • /
    • 2002
  • The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

Determination of RAM-D Requirement for Vehicle System (기동장비 RAM-D 요구조건 설정)

  • 한상철;서준모
    • Proceedings of the Korean Reliability Society Conference
    • /
    • 2001.06a
    • /
    • pp.503-511
    • /
    • 2001
  • 신규 개발되는 기동장비의 RAM-D 요구조건 설정방법에 관하여 기동 무기체계의 대표적 장비인 전차를 대상으로 연구하였으며, 사용자의 장비운용에 대한 요구 가용 능력 및 운용유지 조건을 고려한 RAM-D 요구조건 설정절차 및 분석 모델을 개발하였다.

  • PDF

Development of RAM in Millimeter Wave Range for RF Stealth (RF 스텔스 효과를 위한 밀리미터 RAM 개발)

  • Choi, Chang-Mook;Lim, Bong-Taeck;Ko, Kwang-Soob
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.13 no.6
    • /
    • pp.1241-1246
    • /
    • 2009
  • In this paper, stealth technology, which minimizes detection from the enemy, was analyzed and it was confirmed that Most RCS reduction comes from shaping and in specific parts, by applying RAM. Therefore, we designed and manufactured RAM that absorbs 98% of electromagnetic wave at 94 GHz with 17dB of radar absorption property to minimize RCS at milimeter wave range. As a result, we had 62% reduction in the detection range from the enemy by using developed RAM.

Development of RAM in Millimeter Wave Range for RF Stealth (RF 스텔스를 위한 밀리미터 RAM 개발)

  • Choi, Chang-Mook;Lim, Bong-Taeck;Ko, Kwang-Soob
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2009.05a
    • /
    • pp.555-558
    • /
    • 2009
  • In this paper, stealth technology is investigated with RCS(Radar Cross Section) reduction to minimize detection range of retroreflective echoes from enemy. Most RCS reduction comes from shaping. RAM(Radar Absorbing Materials) are applied only in areas where there are special problems. Therefore, we designed and fabricated a RAM that has absorption ability higher than 17 dB at 94 GHz for RF stealth in millimeter wave range. As a result, detection range of enemy can be reduced in the 62 percent range by using a developed RAM.

  • PDF

Analysis of Flow and BOD Transport at the Downstream of Nam River Dam Using 2-D and 3-D Semi-coupled Models (2·3차원 준연계 모형을 이용한 남강댐 하류부 흐름 및 BOD 수송 해석)

  • Kim, Ji-Hoon;Song, Chang-Geun;Kim, Young-Do;Seo, Il-Won
    • Journal of Korea Water Resources Association
    • /
    • v.45 no.3
    • /
    • pp.331-347
    • /
    • 2012
  • The downstream of the Nam River Dam is crucial region for long-term water resource planning for Busan and Gyeongnam Province. Thus, the analysis of flow behavior and water quality is necessary for the sustainable surface water management and the control of pollutant source. In this study, the flow field and BOD transport at the downstream of Nam River Dam were analyzed by incorporating 2-D water quality model, RAM4 and 3-D water quality model, WASP with the hydrodynamic model, RAM2 and EFDC, respectively. The application of 2-D flow analysis model, RAM2 showed that velocity distributions at the five transverse sections of the meandering part closely followed the measured values by ADCP, and the flow field and overflow characteristic at the submerged weir showed satisfactory performance compared with the result of 3-D EFDC model. In addition, the BOD concentration field obtained by RAM2-RAM4 coupled modeling was in good agreement with the result by EFDC-WASP model throughout the computational domain. The hydrodynamic characteristic and water quality at the downstream reach of Nam River Dam are mainly influenced by the Dam discharge, and the water quantity is closely related to the water quality control and fishery environment at the lower part of Nakdong River. Therefore, when further quantitative analysis is necessary regarding these issues, 2-D semi-coupled modeling is recommended in terms of computational effectiveness and model application aspect.

A study on the computer-controlled measuring device of complex dielectric constant (복소유전률 측정장치의 연구개발 - 컴퓨터제어 복소유전률 측정장치 -)

  • Nam, J.R.;Eum, S.O.;Kang, D.H.
    • Proceedings of the KIEE Conference
    • /
    • 1993.07b
    • /
    • pp.1206-1208
    • /
    • 1993
  • This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

  • PDF

A Row Decoder Design and Simulation Considering The Characteristics of PoRAM (PoRAM의 특성을 고려한 행 디코더 설계 및 시뮬레이션)

  • Park, Yu-Jin;Kim, Jung-Ha;Cho, Ja-Young;Lee, Sang-Sun
    • Proceedings of the IEEK Conference
    • /
    • 2006.06a
    • /
    • pp.659-660
    • /
    • 2006
  • The low crosstalk row-decoder is studied for PoRAM applications. Because polymer-based memories can be more densely integrated than established silicon-based ones, PoRAM is highly sensitive for the crosstalk problem. To overcome the problem and to suggest the suitable decoder for PoRAM, this paper shows the comparison of the row-path characteristics for both the 2-stage dynamic logic decoder and the 2-stage static logic decoder. Moreover, to suppress the Glitch effect which is observed by using the static logic decoder, the Master-Slave(M/S) D-Flip/Flop(D-F/F) is applied as a deglitch. Finally, the improved output result of the 2-stage static logic decoder with the M/S D-F/F is shown..

  • PDF