• Title/Summary/Keyword: Quality Output

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FPGA Implementation of LSB-Based Steganography

  • Vinh, Quang Do;Koo, Insoo
    • Journal of information and communication convergence engineering
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    • v.15 no.3
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    • pp.151-159
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    • 2017
  • Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

Hardware-Aware Rate Monotonic Scheduling Algorithm for Embedded Multimedia Systems

  • Park, Jae-Beom;Yoo, Joon-Hyuk
    • ETRI Journal
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    • v.32 no.5
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    • pp.657-664
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    • 2010
  • Many embedded multimedia systems employ special hardware blocks to co-process with the main processor. Even though an efficient handling of such hardware blocks is critical on the overall performance of real-time multimedia systems, traditional real-time scheduling techniques cannot afford to guarantee a high quality of multimedia playbacks with neither delay nor jerking. This paper presents a hardware-aware rate monotonic scheduling (HA-RMS) algorithm to manage hardware tasks efficiently and handle special hardware blocks in the embedded multimedia system. The HA-RMS prioritizes the hardware tasks over software tasks not only to increase the hardware utilization of the system but also to reduce the output jitter of multimedia applications, which results in reducing the overall response time.

Optimal Switching Pattern for PWM AC-AC Converters Using Bee Colony Optimization

  • Khamsen, Wanchai;Aurasopon, Apinan;Boonchuay, Chanwit
    • Journal of Power Electronics
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    • v.14 no.2
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    • pp.362-368
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    • 2014
  • This paper proposes a harmonic reduction approach for a pulse width modulation (PWM) AC-AC converters using Bee Colony Optimization (BCO). The optimal switching angles are provided by BCO to minimize harmonic distortions. The sequences of the PWM switching angles are considered as a technical constraint. In this paper, simulation results from various optimization techniques including BCO, Genetic Algorithm (GA), and Particle Swarm Optimization (PSO) are compared. The test results indicate that BCO can provide a better solution than the others in terms of power quality and power factor improvement. Lastly, experiments on a 200W AC-AC converter confirm the performance of the proposed switching pattern in reducing harmonic distortions of the output waveform.

New Configuration of 36-pulse Voltage Source Converter Using Pulse-Interleaving Auxiliary Circuit (펄스다중화 보조회로를 이용한 새로운 구조의 36-펄스 전압원 컨버터)

  • Jon Young-Soo;Baek Seung-Taek;Han Byung-Moon
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.54 no.5
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    • pp.238-244
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    • 2005
  • This paper proposes a new configuration of 36-pulse voltage source converter which consists of two 6-pulse bridges and a pulse-interleaving auxiliary circuit. The system topology of proposed converter was derived to increase the pulse number of converter output voltage without increasing the number of 6-pulse bridges. The gate pulse generation was analyzed using the theoretical approach of multi-pulse switching converter, The operational feasibility of proposed system was verified by computer simulations with PSCAD/EMTDC software and experimental works with 2kVA hardware prototype. The proposed converter can be widely used for the uninterruptible power supply, the power quality compensator, and the distributed power generation, such as solar and fuel cell power system.

Improvement of Power Quality of Single-phase Utility Interactive Inverter using Repetitive Controller (반복제어기를 적용한 단상 계통연계형 인버터의 전력품질 개선)

  • Kim, J.H.;Mok, H.S.;Choe, G.H.;Lee, J.W.;Chung, G.B.;Lee, J.M.;Cho, Y.H.
    • Proceedings of the KIPE Conference
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    • 2007.11a
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    • pp.11-14
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    • 2007
  • In recent years, installation of the new and renewable energy system is rapidly increasing. Because the new and renewable energy system is a practical distributed generation system to save energy resources and to keep environments clean. Conventional single-phase utility interactive inverter controls output current by using PI current controller. However, this method is insufficient to suppress harmonic current resulted from nonlinear loads in grid line. In this paper, in order to suppress periodic waveform distortion and improve THD(Total Harmonic Distortion), new type current controller added a parallel repetitive controller is proposed and then performance of the proposed controller was verified with computer simulation.

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Design of an Image Interpolator for Low Computation Complexity

  • Jun, Young-Hyun;Yun, Jong-Ho;Park, Jin-Sung;Choi, Myung-Ryul
    • Journal of Information Processing Systems
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    • v.2 no.3 s.4
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    • pp.153-158
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    • 2006
  • In this paper, we propose an image interpolator for low computational complexity. The proposed image interpolator supports the image scaling using a modified cubic convolution interpolation between the input and output resolutions for a full screen display. In order to reduce the computational complexity, we use the difference in value of the adjacent pixels for selecting interpolation methods and linear function of the cubic convolution. The proposed image interpolator is compared with the conventional one for the computational complexity and image quality. The proposed image interpolator has been designed and verified by Verilog HDL(Hardware Description Language). It has been synthesized using the Xilinx VirtexE FPGA, and implemented using an FPGA-based prototype board.

Identification and Damping of Resonances in Inverter-based Microgrids

  • Afrasiabi, Morteza;Rokrok, Esmaeel
    • Journal of Power Electronics
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    • v.18 no.4
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    • pp.1235-1244
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    • 2018
  • The application of shunt capacitor banks and underground cables typically induces resonance in power distribution systems. In this study, the propagation of resonance in a microgrid (MG) with inverter-based distributed generators (IBDGs) is investigated. If resonances are not properly damped, then the output current of the inverters may experience distortion via resonance propagation due to the adverse effect of resonances on MG power quality. This study presents a conceptual method for identifying resonances and related issues in multi-inverter systems. For this purpose, existing resonances are identified using modal impedance analysis. However, some resonances may be undetectable when this method is used. Thus, the resonances are investigated using the proposed method based on the frequency response of a closed-loop MG equivalent circuit. After analyzing resonance propagation in the MG, an effective virtual impedance damping method is used in the IBDG control system to damp the resonances. Results demonstrate the effectiveness of the proposed method in compensating for existing resonances.

An Interactive Approach to Multiple Response Optimization (다중반응최적화를 위한 상호교호적 접근법)

  • Lee, Pyoungsoo;Park, K. Sam
    • Journal of the Korean Operations Research and Management Science Society
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    • v.40 no.3
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    • pp.49-61
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    • 2015
  • We study the problem of multiple response optimization (MRO) and focus on the selection of input levels which will produce desirable output quality. We propose an interactive multiple objective optimization approach to the input design. The earlier interactive methods utilized for MRO communicate with the decision maker only using the response variable values, in order to improve the current response values, thereby resulting in the corresponding design solution automatically. In their interaction steps of preference articulation, no account is taken of any active changes in design variable values. On the contrary, our approach permits the decision maker to change the design variable values in its interaction stage, which makes possible the consideration of the preference or economics of the design variable side. Using some typical value functions, we also demonstrate that our method converges reasonably well to the known optimal solutions.

A case study on improving the performance of R&D org. using software configuration method (소프트웨어 형상관리 기법을 이용한 R&D조직 성과향상 사례연구)

  • Kim, Byeong-Sam;Jang, Byeong-Man;Kim, Jeong-Han
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2007.11a
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    • pp.408-412
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    • 2007
  • This paper presents, with some actual cases of employing clear case, as a R&D project configuration management tool, a new methodology for the evaluation and enhancement of project performance in R&D organization. This methodology enables you to forecast future results of the project with story telling skill, to innovate R&D project execution using the concept of Technology Supply Chain with global R&D human resources, to improve the performance of each development stage based on the voices of customer, and to enhance the quality of output and to minimize risk of project with timely positioning of R&D human resources.

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SNPAnalyzer: web-based workbench for the SNPs analysis

  • Yoo, Jin-Ho;Seo, Bong-Hee;Kim, Yang-Seok
    • Proceedings of the Korean Society for Bioinformatics Conference
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    • 2003.10a
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    • pp.236-244
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    • 2003
  • Summary: The analysis of human genetic variation is one of the key issues far the understanding of the different drug response among individuals and many programs are developed for this purpose. However, current publicly available programs have so many limitations such as time complexity problem for the analysis of large amount of alleles or SNPs, difficult manipulation for installation, data import, and usage, and low-quality visual output. Here we present workbench for SNP anlaysis, SNPAnalyzer. SNPAnalyzer consists of 3 main modules: 1)Hardy-Weinberg Equilibrium ,2) Haplotype Estimation, and 3) Linkage Disequilibrium. Each module has several different widely-used algorithms for the extensive analysis and can handle large amount of alleles and SNPs with simple format. Analysis results are displayed in user-friendly formats such as table, graph and map. SNPAnalyzer is developed using C and C$^{++}$ and users can easily access through web-interftce. Availability: SNPAnalyzer can be freely implemented at http://www.istech.info/istech/board/login_form.jsp

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