• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1071-1072
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• 2007

인버터 출력단은 구조상 상단락의 위험성이 내재되어있기 때문에 이를 회피하기 위한 Dead time의 적용이 반드시 요구된다. 본 논문에서는 상단락 방지기능을 갖는 출력단의 구조를 사용한 파워 모듈을 설계하고 상단락 방지기능 분석 및 Q3D Extractor와 PSPICE를 사용하여 상단락 방지형 인버터의 출력단기생임피던스의 영향을 고려한 스위칭 동작 특성을 분석하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.176-182
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• 2021

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.