• Journal of Power Electronics
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• 제16권2호
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• pp.490-497
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• 2016

The analysis of the switch status of each unit module of a cascaded multi-level inverter reveals that the working condition of the switch of a chopper arm causes unnecessary switching under the conventional unipolar sinusoidal pulse width modulation (SPWM). With an increase in the number of cascaded multilevel inverters, the superposition of unnecessary switching gradually occurs. In this work, we propose an improved SPWM strategy to reduce switching in cascaded multilevel inverters. Specifically, we analyze the switch state of the switch tube of a chopper arm of an H-bridge unit. The redundant switch is then removed, thereby reducing the switching frequency. Unlike the conventional unipolar SPWM technique, the improved SPWM method greatly reduces switching without altering the output quality of inverters. The conventional unipolar SPWM technique and the proposed method are applied to a five-level inverter. Simulation results show the superiority of the proposed strategy. Finally, a prototype is built in the laboratory. Experimental results verify the correctness of the proposed modulation strategy.

• Journal of Power Electronics
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• 제5권2호
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• pp.142-150
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• 2005

This paper presents a systematic approach to study the carrier based pulse width modulation (PWM) techniques applied to diode-clamped and cascade multilevel inverters by using multi-modulating patterns. This method is based on the description of controllable redundant parameters in the modulating signals. A unified mathematical formulation is presented for carrier based PWM methods, which obtains outputs similar to the corresponding space vector PWM. A full and separate control of the fundamental voltage, vector redundancies and phase redundancies can be obtained in the carrier based PWM. In this paper, the proposed PWM method and corresponding algorithm for generating multi-modulating signals will be formulated and demonstrated by our simulations.

• Journal of Power Electronics
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• 제16권4호
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• Journal of Power Electronics
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• 제10권2호
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• 전력전자학회논문지
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• 제15권1호
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• pp.43-51
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• 2010

본 논문에서는 고전압 전동기 가변속 장치인 H-브릿지 멀티레벨(H-Bridge Multi-Level; HBML) 인버터를 이용한 유도 전동기 벡터 제어시 인버터의 출력 전압 위상 지연 현상을 해석하고 전류 제어기의 보상 기법을 제시하였다. Phase-Shifted Pulse Width Modulation (PSPWM) 기법을 적용한 HBML 인버터는 개별 인버터 모듈이 독립적으로 동작할 수 있어서 확장성과 모듈화 능력이 향상되는 장점이 있다. 그러나 이러한 PSPWM을 적용한 HBML 인버터는 기준 전압과 실제 전압 사이에 위상 차이가 있기 때문에 출력 주파수에 대한 샘플링 주파수의 비율이 충분하지 않은 고속 영역에서 전류 제어기를 불안정하게 하는 원인이 된다. 전류 제어기의 불안정성은 기준 전압과 출력 전압의 위상 차이를 보상하는 제안된 방법을 추가함으로써 제거하였다. 본 방법은 인버터의 스위칭 주파수가 낮고, 전동기 속도가 높은 조건에서 PSPWM을 이용한 HBML 인버터 시스템에 효과적이며, 13레벨로 구성된 HBML 인버터로 구동되는 6,600[V] 1,400[kW] 유도전동기 실험을 통해 제안된 방법의 타당성을 입증하였다.

• Journal of Power Electronics
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• 제11권6호
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• pp.837-845
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• 2011

This paper proposes phase current reconstruction techniques for two-phase two-leg and two-phase four-leg inverters using a single current sensor. In the proposed methods, one phase current is sampled simultaneously with a particular branch current by using only one current sensor, and then current reconstruction algorithms are applied to extract the information on two phase currents from the sensor output. The sampled current information is periodically updated at the peak and the valley of the triangular carrier waveform in each switching cycle of pulse-width modulation (PWM). The voltage vector spaces where the phase currents can be reconstructed are evaluated. Compared to the existing method using two individual current sensors in two phases, the proposed schemes can save implementation cost since it is possible to remove one current sensor. In addition, the proposed methods are free from gain discrepancy issues between two current sensors. Simulations and experiments show excellent current reconstruction performance of the proposed methods.

• 전기학회논문지
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• 제62권4호
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• pp.502-509
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• 2013

It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

• Journal of Electrical Engineering and Technology
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• 제12권5호
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• pp.1872-1882
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• 2017

Medium voltage drive systems driven by high-power multi-level inverters operating at low switching frequency can reduce the switching losses of the power device and increase the output power. Employing subsection synchronous current harmonic minimum pulse width modulation (CHMPWM) technique can maintain the total harmonic distortion of current at a very low level. It can also reduce the losses of the system, improve the system control performance and increase the efficiency of DC-link voltage accordingly. This paper proposes a subsection synchronous CHMPWM approach of active neutral point clamped five-level (ANPC-5L) inverter under low switching frequency operation. The subsection synchronous scheme is obtained by theoretical calculation based on the allowed maximum switching frequency. The genetic algorithm (GA) is adopted to get the high-precision initial values. So the expected switching angles can be achieved with the help of sequential quadratic programming (SQP) algorithm. The selection principle of multiple sets of the switching angles is also presented. Finally, the validity of the theoretical analysis and the superiority of the CHMPWM are verified through both the simulation results and experimental results.

• Journal of Power Electronics
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• 제14권1호
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• pp.61-73
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• 2014

Multiphase machines are characterized by high power density, enhanced fault-tolerant capacity, and low torque pulsation. For a voltage source inverter supplied multiphase machine, the probability of load imbalances becomes greater and unwanted low-order stator voltage harmonics occur. This paper deals with the PWM control of multiphase inverters under unbalanced load conditions and it proposes a novel near-five-vector SVPWM algorithm based on the five-phase six-leg inverter. The proposed algorithm can output symmetrical phase voltages under unbalanced load conditions, which is not possible for the conventional SVPWM algorithms based on the five-phase five-leg inverters. The cause of extra harmonics in the phase voltages is analyzed, and an xy coordinate system orthogonal to the ${\alpha}{\beta}z$ coordinate system is introduced to eliminate low-order harmonics in the output phase voltages. Moreover, the digital implementation of the near-five-vector SVPWM algorithm is discussed, and the optimal approach with reduced complexity and low execution time is elaborated. A comparison of the proposed algorithm and other existing PWM algorithms is provided, and the pros and cons of the proposed algorithm are concluded. Simulation and experimental results are also given. It is shown that the proposed algorithm works well under unbalanced load conditions. However, its maximum modulation index is reduced by 5.15% in the linear modulation region, and its algorithm complexity and memory requirement increase. The basic principle in this paper can be easily extended to other inverters with different phase numbers.

• Journal of Power Electronics
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• 제16권4호
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• pp.1407-1414
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• 2016

Unlike existing pulse-width modulation (PWM) techniques, such as sinusoidal PWM and random PWM, the wavelet PWM (WPWM) technique based on a Harr wavelet function can achieve a high fundamental component for the output voltage, low total harmonic distortion, and simple digital implementation. However, the original WPWM method lacks output voltage control. Thus, the practical application of the WPWM technique is limited. This study proposes an improved WPWM technique that can regulate output voltage amplitude with the addition of a parameter. The relationship between the additional parameter and the output voltage amplitude is analyzed in detail. Experimental results verify that the improved WPWM exhibits output voltage control in addition to all the merits of the WPWM technique.