• Journal of Power Electronics
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• 제16권2호
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• pp.473-479
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• 2016

In this paper, the PSC PWM method is chosen as the optimal modulation method for a 20MW VSC HVDC, with consideration of the harmonic distortion of the output voltage, the switching frequency, and the control implementation difficulty. In addition, a new PSC PWM method is proposed in order to achieve an easy application and to solve the redundant control problems encountered in the previous PSC PWM method. To verify the proposed PSC PWM method, PSCAD/EMTDC simulations for an 11-level MMC RTDS HILS test and an 11-level MMC prototype converter test were performed. As can be seen from the results of these tests, the proposed PSC PWM method shows good results in an 11-level MMC with redundant sub-modules.

• Journal of Power Electronics
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• 제18권6호
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• pp.1627-1633
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• 2018

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC $1{\mu}m$ 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.

• Journal of information and communication convergence engineering
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• 제8권2호
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• pp.205-211
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• 2010

In this study, a Magnetic stimulation Pulse Train control technique is introduced and applied to Flyback converter operating in discontinuous conduction mode. In contrast to the conventional pulse width modulation control scheme, the principal idea of a Magnetic stimulation Pulse Train is to achieve output voltage regulation using high and low power pulses. The proposed technique is applicable to any converter operating in discontinuous conduction. However, this work mainly focuses on Flyback topology. In this paper, the main mathematical concept of the new control algorithm is introduced and simulations as well as experimental results are presented.

• Journal of Power Electronics
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• 제12권5호
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• pp.708-714
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• 2012

This paper presents a new interleaved pulse-width modulation (PWM) boost-flyback converter to achieve power factor correction (PFC) and regulate DC bus voltage. The adopted boost-flyback converter has a high voltage conversion ratio to overcome the limit of conventional boost or buck-boost converter with narrow turn-off period. The proposed converter has wide turn-off period compared with a conventional boost converter. Thus, the higher output voltage can be achieved in the proposed converter. The interleaved PWM can further reduce the input and output ripple currents such that the sizes of inductor and capacitor are reduced. Since boundary conduction mode (BCM) is adopted to achieve power factor correction, power switches are turned on at zero current switching (ZCS) and switching losses are reduced. The circuit configuration, principle operation, system analysis, and design consideration of the proposed converter are presented in detail. Finally, experiments conducted on a laboratory prototype rated at 500W were presented to verify the effectiveness of the converter.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.398-401
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• 2011

본 논문에서는 고효율의 CMOS PWM DC-DC 벅 변환기를 설계하였다. 설계된 CMOS PWM DC-DC 벅 변환기는 입력전압(3.4-3.9V)로부터 일정한 출력전압(1-2.8V)을 생성한다. Inductor-based 방식을 택하였고, 제어 대상은 전류이며, Pulse Width Modulation(PWM) 모드로 동작한다. 회로 구성은 Power Switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator, Modulator 등 이다. 제안된 CMOS PWM DC-DC 벅 컨버터는 Switching Frequency가 약 1MHz이고, 부하 전류가 약 40mA이상부터 CCM동작을 하며 100mA일 때 98.71%의 최대 효율을 갖는다. 또한, 출력전압 리플은 0.98mV이다(입력전압 3.5V, 출력전압 2.5V 기준). 제안된 회로의 검증을 위해 CMOS $0.18{\mu}m$ 공정을 이용하여 시뮬레이션을 수행하였다.

• 전기학회논문지
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• 제65권10호
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• pp.1655-1663
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• 2016

Recently the researches on Modular Multi-level Converter (MMC) are being highlighted because high quality and efficient power transmission are key issues in the High Voltage Direct Current (HVDC) transmission system. This paper proposes an improved pre-charging method for the sub-module capacitors in MMC that operates in Nearest Level Control (NLC) modulation. The proposed method does not require additional circuits or Pulse Width Modulation (PWM) techniques. The feasibility of proposed method was verified through computer simulations for a scaled 3-phase 10kVA MMC with 12 sub-modules per each arm. Hardware experiments with a scaled prototype were performed in the lab to confirm the simulation results.

• Journal of Electrical Engineering and Technology
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• 제5권3호
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• pp.477-483
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• 2010

This paper is studied on a novel buck-boost isolated converter for high efficiency and high power factor. The switching devices in the proposed converter are operated by soft switching technique using a new quasi-resonant circuit, and are driven with discontinuous conduction mode (DCM) according to pulse width modulation (PWM). The quasi-resonant circuit makes use of a step up-down inductor and a loss-less snubber capacitor. The proposed converter with DCM also simplifies the requirement of control circuit and reduces a number of control components. The input ac current waveform in the proposed converter becomes a quasi sinusoidal waveform in proportion to the magnitude of input ac voltage under constant switching frequency. As a result, it is obtained by the proposed converter that the switching power losses are low, the efficiency of the converter is high, and the input power factor is nearly unity. The validity of analytical results is confirmed by some simulation results on computer and experimental results.

• Journal of Power Electronics
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• 제17권3호
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• pp.641-652
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• 2017

This paper proposes a cost-effective topology to drive a three-phase open-end load based on a five-leg indirect matrix converter (IMC) and a space vector modulation (SVM) method. By sharing an inverter leg with two load terminals, the proposed topology can reduce the number of power switches when compared to topologies based on a direct matrix converter or a six-leg IMC. The new SVM method uses only the active vectors that do not produce common-mode voltage (CMV), which results in zero CMV across the load phase and significantly reduces the peak value of the CMV at the load terminal. Furthermore, the proposed drive system can increase the voltage transfer ratio up to 1.5 and provide a superior performance in terms of an output line-to-line voltage with a three-level pulse-width modulation waveform. Simulation and experimental results are given to verify the effectiveness of the proposed topology and the new SVM method.

• 전력전자학회논문지
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• 제19권6호
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• pp.488-493
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• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• 전기전자학회논문지
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• 제23권3호
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• pp.1104-1107
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• 2019

본 논문에서는 데드 타임을 줄여 전력 효율을 높이기 위해 데드 타임 제어기를 이용한 웨어러블 AMOLED 디스플레이용 DC-DC 부스트 변환기를 제안한다. 또한, 본 변환기에서는 경부하에서 전력 효율을 높이고 출력 전압 리플을 감소시키기 위해 PWM-SPWM (set-time variable pulse width modulation) 듀얼 모드를 이용한다. 제안하는 회로는 $0.18{\mu}m$ BCDMOS 공정을 이용하여 시뮬레이션을 한 결과 1 mA~70 mA의 부하 전류 범위에서 39%~96%의 전력 효율과 2 mV의 리플 전압을 가졌다. 본 회로의 전력 효율은 PWM-SPWM 방식보다 최대 2% 상승하였고, PWM 방식보다 최대 8% 상승하였다.