• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.341-352
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• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• Journal of Korean Society of Environmental Engineers
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• v.31 no.4
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• pp.278-286
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• 2009

In this study, four natural Mn oxides ($NMO_1-NMO_4$) was characterized using x-ray diffraction, scanning electron microscopy, and their removal efficiency for 1-naphthol (1-NP) in aqueous phase, using batch reactor, was investigated. The results were compared with one another and a synthetic manganese oxide, birnessite. The NMOs have a various Mn minerals including pyrolusite (${\beta}-MnO_2$), cryptomeltane (${\alpha}-MnO_2$) as well as birnessite (${\delta}-MnO_2$) depending on their sources, which results in different removal efficiencies (removals, kinetics) and reaction types (sorption or oxidative-transformation). The comparative study showed that $NMO_1$ (electrolytic Mn oxide) have a higher removal efficiency for 1-NP via oxidative-transformation compared to birnessite. The 1-NP removals by NMOs were followed by pseudo-first order reaction, and the surface area-normalized specific rate constants ($K_{surf},\;L/m^2$ min) determined were in order of $NMO_1(3.31{\times}10^{-3})$>${\delta}-MnO_2(1.48{\times}10^{-3}){\fallingdotseq}NMO_3(1.46{\times}10^{-3})$>$NMO_2(0.83{\times}10^{-3})$>$NMO_4(0.67{\times}10^{-3})$. From the solvent extraction experiments with the Mn oxide precipitates after reaction, it was observed that the oxidative-transformation rates of 1-NP were in order of $NMO_1{\fallingdotseq}{\delta}-MnO_2$>$NMO_3$>$NMO_4{\gg}NMO_2$ and the analysis of HPLC chromatogram and UV-Vis. absorption ratios ($A_{2/4}$, $A_{2/6}$) on the supernatant confirmed that the reaction products were oligomers formed by oxidative-coupling reaction. Results from this study proved that natural Mn oxide (except $NMO_2$) used in this experiment can be effectively applied for the removal of naphthols in aqueous phase, and the removal efficiencies are depending on the surface characters of the Mn oxides.