• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.757-760
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• 2005

The technology of rapid prototyping (RP) is used for design verification, function test and fabrication of prototype. The current issues in RP are improvement in accuracy and application of various materials. In this paper, a hybrid rapid prototyping system is introduced which can fabricate nano composites using various materials. This hybrid system adopts RP and machining process, so material deposition and removal is performed at the same time in a single station. As examples, micro gears and a composite scaffold were fabricated using photo cured polymer with nano powders such as carbon black and hydroxyapatite. From the micro gear samples the hybrid RP technology showed higher precision than those made by casting or deposition process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.578-582
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• 1996

Verification of STL is essential in RP. In the study, triangle based non-manifold geometric modeling that can check intersection between triangles was used to vilify STL. The method proposed in this study can be applied at the most general case and very useful, but has a penalty on computing thime of O(n$^2$)

• Korean Journal of Computational Design and Engineering
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• v.8 no.4
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• pp.212-221
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• 2003

In order to reduce the lead-time and cost, the technology of rapid prototyping (RP) has been widely used. A new rapid prototyping process, transfer-type variable lamination manufacturing process by using expandable polystyrene foam (VLM-ST), has been developed to reduce building time, apparatus cost and additional post-processing. At the same time, VLM Slicer, the CAD/CAM software for VLM-ST has been developed. In this study, algorithms for accuracy improvement of VLM-ST, which include offset and overrun of a cutting path and generation of a reference shape are developed. Offset algorithm improves cutting accuracy, overrun algorithm enables the VLM-ST process to make a shape of sharp edge and reference shape generation algorithm adds additional shape which makes off-line lamination easier. In addition, proposed algorithms are applied to practical CAD models for verification.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.83-86
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• 1997

Even as many methods and technologies have been introduced on data generation, parts orientation and layer slicing to acquire the rapid prototyping(RP) parts that have useful surface to satisfy customers' needs such as stylingldesign verification directionlindirect tooling directly from the RP machine, these trials continue to suffer from the surface roughness due to the build characteristics of RP technology. A new postprocess finishing method is suggested in this paper to overcome the surface roughness problem on the surface of the RP parts. To prevent deterioration of dimensional accuracy from the conventional grinding-only, and coating-grinding methods, 4-step surface finishing process is applied. To satisfy the various requirements from the RP oriented industrial f elds, effective procedure, coating material, grmd~ng tools and methods are employed.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.10
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• pp.46-55
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• 1996

As industrial standard data, the STL format which approximates three dimensional CAD model to triangular facets, is used for RP(Rapid Prototyping) system in recent days. Because most RP system take the only form of two dimensional line segments as an input stream inspite of its imperfectness while converting into STL format, a CAD model is converted into a standard industrial format which is composed of many triangular facets. The error verifying process is composed of four main steps, and these are 1) Remove facets with two or more vertices equal to each other. 2) Fix overlapping error such as more than three facets adjacent to anedge. 3) Fill holes in the mesh by using Delaunay triangulation method. 4) Correct the wrong direction and normal vectors. This paper is concerned with serching the mentioned errors in advance and modifying them.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.04a
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• pp.597-601
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• 1996

Nowadays, the STL format, industrial standard data, which approximates three dimensional CAD model to triangular facets, is used for RP(Rapid Prototyping) system. Because most RP machine is accpted to only two dimensional line segments, but some STL translators are sometimes poorly implemented. The error verifying process is as follows. 1) Remove facets with two or more vertices equal to each other. 2) Fix overlapping error such as more than three facets adjacent to an edge. 3) Fill holes in the mesh by using Delaunay triangulation method. 4) Repair wrong direction and value of normal vectors. This paper is concerned with searching the mentioned errors in advance and modifying them.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.11
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• pp.2409-2414
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• 2002

The surfaces of prototypes become rough due to the stair-stepping which is the inevitable phenomenon in the Rapid Prototypes are not used only for the verification of feature. The grinding, coating, or the composition of them is a main operation in post-processing in which lots of costs and long build time are needed. The solution is proposed to increase the efficiency of rapid prototyping by minimizing or removing the composition of them is a main operation in post-processing in which lots of costs and long build time are needed. the solution is proposed to increase the efficiency of rapid prototyping by minimizing or removing the regions for post-processing. the factors to cause the surface roughness and their effects are analyzed through the experiments. Software modules are developed to predict the surface roughness of each face in the prototyping with the result. An experimental compensation method is developed to apply the modules to various RP equipments, materials and build styles. The build direction is searched with use of genetic algorithm to maximize the total areas of the surface of which roughness is better than the user-defined value.

• Proceedings of the IEEK Conference
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• summer
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• pp.281-284
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• 2004

In this paper, a verification method and model for a PCI-Express device are described. PCI-Express technology is one of new I/O interconnection technologies which is intended to replace conventional PCI based technology, and is introduced by PCI-SIG in 2002. For a fast prototyping, a verification suite which includes a behavioral model and stimuli is needed before actual design is finished. And also it should be simple in structure and accurate enough to verify the design. In this paper, an Early Verification Suite (EVS) which complies with PCI-Express protocol is developed and tested.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.7
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• pp.97-105
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• 2002

The use of rapid prototyping (RP) has reduced time to market, cut total costs and improved product quality by giving design and manufacturing teams the opportunity to verify and fine tune designs before committing them to expensive tooling and fabrication. In order to improve their unique characteristics according to the working principles, Variable Lamination Manufacturing process (VLM-ST) and corresponding CAD/CAM software (VLM-Slicer) is developed. The objective of this study is to improve the accuracy of VLM-ST process, and it can be done by offset fur cutting error correction, cutting path overrun fur sharp edge and reference shape generation for off-line stacking. It has been shown that, through the verification experiments for given practical shapes, the proposed algorithms are effective for diverse categories of three-dimensional shapes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.869-872
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• 2008

This paper presents the VHDL implementation procedure of the passive RFID tag in Ultra High Frequency RFID system. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation on prototyping board. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of the interrogation rate. Also with UART communication, verify a inventory Round in Gen2 Protocol. The verification results with the fastest data rate, 640kbps, and multi tags environment scenario show that the implemented tag spend 1.4ms transmitting the 96bits EPC to reader.