• International Journal of CAD/CAM
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• v.3 no.1_2
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• pp.85-95
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• 2003

During the design of dies and molds, the cavity of the object is obtained by subtracting it from a surrounding rectangular block. This box is subsequently split into two halves by the parting surface. Similar problems also occur in some RP processes such as LOM, SGC, SLS and 3DP where the machine produces a block inside which the prototype is buried. Determining the orientation of the object inside the box and the corresponding parting surface taking appropriate constraints into account have been addressed by several researchers. However, given the parting surface, the problem of splitting the box development of a software package called OptiLOM (now a module of an RP software Magics 8.0), the authors realized non-triviality of this problem since the loop can spread over as many as 5 faces of the box. In this paper, the authors have tried to bring out the importance of this problem and have presented their algorithm to solve it.

• Journal of IKEEE
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• v.24 no.2
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• pp.486-491
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• 2020

ARM Cortex-M0 DesignStart provided by ARM is cost-free design development suit targeting for designing and prototyping SoC with Cortex-M0 core. In this paper, we presents a method how to implement a custom system design using ARM Cortex-M0 DesignStart. First, hardware elements for ARM Cortex-M0 DesginStart is analyzed focusing on bus and memory map, and next software toolchain is explained to clarify the translating process from high level language to binary machine language. As an example of the custom system, UART system operated with Cortex-M0 is designed and simulated.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Journal of computational fluids engineering
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• v.21 no.3
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• pp.39-47
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• 2016

We conducted a multi-stage optimization to secure the desired performance of a centrifugal fan for home appliance in an early stage of product development. In optimization, the static pressure at the outlet of the fan is chosen as an objective function that is to be maximized, providing the required flow rate at the operating point of the fan. The optimization procedure begins with parameters for an initial baseline fan design. The baseline design is optimized by using a commercial optimization package. Accordingly, the corresponding blade models with a set of geometrical parameters are generated. Flow through a fan is simulated by solving the Reynolds-averaged Navier-Stokes equations. A multi-stage optimization scheme is employed to determine the family of optimum values for the parameters, leading to the pressure increase at the outlet of the fan. To validate the numerically obtained optimal design parameters, we fabricated the three types of fans using rapid prototyping and assessed the performance using a fan tester. Experimental results show that the design parameters at each stage satisfy the goal of optimization. The multi-stage optimization process turned out to be a useful tool in the development of a centrifugal fan.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2009.05a
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• pp.278-281
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• 2009

Selective laser sintering(SLS), a kind of rapid prototyping technology, can provide a process to form many types of coatings. Coated layers by selective laser melting are highly influenced by substrate, powder and laser parameters such as laser power, scan rate, fill spacing and layer thickness. Therefore an attempt to fabricate Fe-Ni-Cr coating on AISI H13 tool steel has been performed by selective laser sintering. In this study, Fe-Ni-Cr coating was produced by experimental facilities consisting of a 200W fiber laser which can be focused to 0.08mm and atmospheric chamber which can control atmospheric pressure with Ar. With power increase or energy density decrease, line width was decreased and line surface quality was improved with energy density increase. Surface quality of coating layer was improved with fill spacing optimization or layer thickness decrease.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.338-343
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• 2006

This paper describes about the design concept and the architecture of an economic VPN system which can perform fast crypto operations with cheap cost. The essence of the proposed system architecture is consisting of the system with two companion chips dedicated to VPN: one chip is a multi-purpose network processor for security machine and the other is a crypto acceleration chip which encrypt and decrypt network packets in a high speed. This study also addresses about some realizations that is required for fast prototyping such as the porting of an operating system, the establishment of compiler tool chain, the implementation of device drivers and the design of IPSec security engine. Especially, the second chip supports the most time consuming block cipher algorithms including 3DES, AES, and SEED and its performance was evaluated.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.334-337
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• 2005

The objective of this research works is to propose a rapid development methodology of small size deep drawing tools for electronic parts utilizing the technology combination of CAE and RP/RT. The technology is applied to the development of deep drawing tools with a drain shape. The final surface of tools is obtained from the evaluation of the formability using the CAE. In order to manufacture the physical prototype of tools fer try-out terming, several fabrication experiments are carried out for three types of rapid tool manufacturing technology. Through the fabrication experiments, the acceptable rapid manufacturing technologies of deep drawing tools with a small size have been proposed.

• The KIPS Transactions:PartD
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• v.11D no.4
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• pp.967-974
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• 2004

An OLAP system is the decision support tool with which a user can analyze the information interactively in the various aspects. However, the traditional existing construction of an OLAP system has the inefficiency problem of increasing the time and cost caused by the frequent changes of the users requirements. In this paper, we analyse existing construction procedure of OLAP systems and propose a prototyping OLAP View based on the star schema which can help and guide the designer In supporting efficiently of users requirements. Through an implementation of S shopping mall using the OLAP View, we show that our proposal is able to support OLAP construction strategy and provide accurate understanding of data resources. With an OLAP View, we can reduce the required time and cost of implementing OLAP system.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.51-53
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• 2012

본 논문에서는 임베디드 소프트웨어 개발 시 .Net Micro Framework를 이용하여 디바이스들의 통신 인터페이스를 소프트웨어 개발자가 좀 더 간단하게 코딩 가능하게 하며 소프트웨어 개발자가 이를 디자이너를 이용하여 그래픽하게 에뮬레이터를 디자인할 수 있도록 임베디드 에뮬레이터 생성 방법을 제시하고 디자인 된 에뮬레이터를 기반으로 자동으로 코딩 없이 에뮬레이터를 생성하는 프로그램을 프로토타이핑 한다. 이때, 소프트웨어 개발자가 그래픽하게 생성한 에뮬레이터 디자인으로 하드웨어 개발자와의 의사소통이 보다 원활해질 수 있다. 또한 본 논문에서 제시하는 임베디드 에뮬레이터 생성 프로그램을 이용하면 추가적인 코딩 작업 없이 디자인 된 에뮬레이터를 기반으로 에뮬레이터가 자동 생성된다. 이로 인하여 .NET Micro Framework에서 제공하는 확장 가능 에뮬레이터와 달리 에뮬레이터를 생성하는데 시간과 노력을 절약할 수 있다. 또한 기존의 개발 과정에서는 기계가 모두 준비되어야 테스팅이 가능했던 것과 달리 기계 없이 에뮬레이터로 테스팅이 가능해짐으로써 개발 기간을 단축시킬 수 있다. 임베디드 에뮬레이터를 이용하면 하드웨어와의 통합 테스트에서 버그의 원인이 하드웨어적인 결함인지 소프트웨어적인 결함인지를 판단 가능하게 하여 디버깅이 용이하게 되며 실제 동작과 원하는 동작을 비교해 볼 수 있다.

• Journal of Korean Academy of Nursing
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• v.49 no.5
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• pp.586-600
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• 2019

Purpose: This study aimed to develop a web-based cost management program for visiting nursing centers (CMP-VNC), using time-driven activity-based costing (TD-ABC), and to analyze effects of the program. Methods: The CMP-VNC was developed using the combined prototyping approach and system developing life cycle method following four stages: need analysis with comprehensive literature reviews and focus group interviews, design and development of program algorithm, evaluation of the developed program validity using experts and users group, and application and effects analysis. The non-equivalent control group pretest-posttest design was used to analyze the effects of the program. The program demonstration was conducted for four weeks with 60 visiting nurses in 35 visiting centers. Results: The web-based program was developed. It has five interfaces with basic and special functions using TD-ABC, namely, input, visiting nursing activity, visiting nursing activity cost, cost efficiency, and cost calculation report. The experimental group showed significantly higher cost perception and cost confidence than control group. Conclusion: We found that the CMP-VNC can be an effective tool to increase visiting nurses' competency of costing and enhance efficiencies of visiting nursing centers.