• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.78-81
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• 2002

We propose a current-mode analog programmable finite-impulse-response (FIR) filter with variable tap circuits. From the circuit simulation, the operation of the 7- tap FIR filter is confirmed. We design and fabricate the 0.0625-step tap circuit using 0.8$\mu\textrm{m}$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to software defined radio (SDR) terminals.

• 조명전기설비학회논문지
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• 제18권6호
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• pp.45-54
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• 2004

일반적으로 반도체 소자의 집적도가 증가함에 따라 기능적 오류 검사 시간이 급격하게 증가하며, 이러한 문제를 해결하기 위해 제조공정에서 패턴 발생기의 사용은 필수적이다. 본 논문에서는 반도체 소자의 기능적 오류를 검사 하기 위한 패턴 발생기의 PLD(Programmable Logic Device) 회로를 설계하였다. 이러한 모든 사항은 시뮬레이션을 통하여 회로의 동작과 기능을 검증하였으며, 만족할만한 결과를 얻었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.5-8
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• 2001

In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

• 융합신호처리학회논문지
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• 제6권3호
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• pp.134-142
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• 2005

전류모드 CMOS 회로기반 다치 논리 회로가 최근에 구현되고 있다. 본 논문에서는 4-치 Unary 다치 논리 함수를 전류모드 CMOS 논리 회로를 사용하여 합성하였다. 전류모드 CMOS(CMCL)회로의 덧셈은 각 전류 값들이 회로비용 없이 수행될 수 있고 또한 부의 논리 값은 전류흐름을 반대로 함으로써 쉽게 구현이 가능 하다. 이러한 CMCL 회로 설계과정은 논리적으로 조합된 기본 소자들을 사용하였다. 제안된 알고리듬을 적용한 결과 트랜지스터의 숫자를 고려하는 기존의 기법보다 더욱 적은 비용으로 구현할 수 있었다. 또한 비용-테이블 기법의 대안으로써 Unary 함수에 대해서 범용 UUPC(Universal Unary Programmable Circuit) 소자를 제안하였다.

• 한국정보통신학회논문지
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• 제19권10호
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• pp.2373-2379
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• 2015

우리나라 최초의 정지궤도 기상위성인 천리안 위성은 고속/저속 전송자료 서비스(HRIT/LRIT: High/Low Rate Information Transmission)를 통해 기상정보를 무료로 제공하고 있다. 본 논문은 천리안 위성의 기상정보를 수신할 수 있는 개인용 PC 기반 보급형 기상정보 수신시스템을 구축하는데 필수적인 기상정보 데이터 수신회로 개발을 소개한다. 기상정보 데이터 수신회로는 HRIT/LRIT 서비스 데이터 유닛에 대해 물리 계층과 데이터 링크 계층에 대응하는 작업을 수행한다. 이를 위해 기상정보 데이터 수신회로는 Viterbi 디코더, Sync. word 감지회로, Derandomizer, Reed-Solomon 디코더 등을 포함하고 수신된 기상정보 데이터를 호스트 PC에 제공하기 위해 PCI Express 전송 방식을 지원한다. 개발된 기상정보 데이터 수신회로는 FPGA(field programmable gate array)를 이용하여 구현되었으며 시뮬레이션과 실제 하드웨어를 통하여 그 기능이 검증되었다.

• 조명전기설비학회논문지
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• 제21권9호
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• pp.39-46
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• 2007

This paper presents a programmable single-phase ac power source that provides a sinusoidal output voltage with an adjustable output amplitude and frequency over a wide range as well as an arbitrary waveform. The ac power source under consideration have a linear power amplifier. The desired output values can be programmed with a personal computer. The power source operates at 220[V]/60[Hz] mains and the output voltage is isolated from the input circuit. The system consists mainly of a power converter to generate and amplify the waveform signal, a controller to control the desired output signal and measure the output parameters, and a control program to set the desired output and display the values. The prototype ac power source was constructed and tested with the results demonstrating a good performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.208-211
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• 2000

This paper describes the design of a CMOS frequency synthesizer using programmable frequency divider with novel architecture. A novel architecture of programmable divider can be producted all of integer-N and fabricated by 0.65$\mu\textrm{m}$ 2-poly, 2-metal CMOS technology. Frequency synthesizer is simulated by 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS technology. This circuit has settling time of 1.5${\mu}\textrm{s}$ and power consumption of 70㎽. Operating frequency of the frequency synthesizer is 820MHz∼l㎓ with a 2.5V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.55-58
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• 1998

Recently, neural networks with self-adaptability like human brain have attracted much attention. It is desirable for the neuron-function to be implemented by exclusive hardware system on account of huge quantity in calculation. We have proposed a novel neuro-device composed of a MFSFET(ferroelectric gate FET) and oscillation circuit with CUJT(complimentary unijuction transistor) and PUT(programmable unijuction transistor). However, it is difficult to preserve ferroelectricity on Si due to existence of interfacial traps and/or interdiffusion of the constitutent elements, although there are a few reports on good MFS devices. In this paper, we have simulated CUJT and PUT devices instead of fabricating them and composed oscillation circuit. Finally, we have resented, as an approach to the MFSFET neuron circuit, adaptive learning function and characterized the elementary operation properties of the pulse oscillation circuit.

• Nuclear Engineering and Technology
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• 제48권5호
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• pp.1192-1205
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• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.