• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.28-39
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• 2007

This paper presents a programmable RF DFT (Radio Frequency Design-for-Testability) circuit for low noise amplifiers. We have developed a new on-chip RF DFT circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements [1, 2]. This circuit is extremely useful for today's RFIC devices in a complete RF transceiver environment. The DFT circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip DFT circuit can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz low noise amplifiers for GSM, Bluetooth and IEEE802.11g standards. The circuit is simple and inexpensive.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.198-206
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• 2011

This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with $0.18-{\mu}m$ BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1004-1007
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• 2005

This paper presents a programmable RF BIST (Built-in Self-Test) circuit for low noise amplifiers. We have developed a new on-chip RF BIST circuit that measures RF parameters of low noise amplifier (LNA) using only DC measurements. The BIST circuit contains test amplifier with programmable capacitor banks and RF peak detectors. The test circuit utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the mathematical equations. Our on-chip BIST can be self programmed for 1.8GHz, 2.4GHz and 5.25GHz LNA for GSM, Bluetooth and IEEE802.11g standards.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.253-256
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• 2002

A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.730-736
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• 1995

This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

• Journal of IKEEE
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• v.17 no.3
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• pp.324-331
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• 2013

In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• The Journal of the Acoustical Society of Korea
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• v.5 no.3
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• pp.13-20
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• 1986

본 논문은 신호처리가 가능한 2진 로가리즘 상수를 발생시키기 위한 programmable variable-rate up/down 계수기의 설계를 기술한다. 2진수에 대한 밑수가 2인 로가리즘 계승의 적용은 결 과적으로 오차가 발생한다. log\sub 2\(1+χ)-χ에 의해 정의된 것처럼 log\sub 2\(1+χ)에서의 오차는 직선의 집합으로 갖게된다. 계수기 rate는 직선의 기울기에 비례한다. 그러므로 신호처리가 가능한 2진 로가리즘 상수는 programmable 계수기를 사용함으로써 쉽게 발생될 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.13-21
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• 2011

In this paper, the CMOS programmable interface circuit for MEMS gyroscope is presented, and evaluated with the MEMS sensing element. The circuit includes the front-end charge amplifier with 10 bit programmable capacitor arrays, 9 bit DAC for accurate offset calibration, and 10 bit PGA for accurate gain calibration. The self oscillation loop with automatic gain control operates properly. The offset error and gain error after calibration are measured to be 0.36 %FSO and 0.19 %FSO, respectively. The noise equivalent resolution and bias instability are measured to be 0.016 deg/sec and 0.012 deg/sec, respectively. The calibration capability of this circuit can reduce the variations of the output offset and gain, and this can enhance the manufacturability and can improve the yield.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.977.2-980
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• 1993

The fuzzifier circuit DPFC 7 is presented. Its features are: programmable membership function, CMOS digital interface, analog and current mode internal processing and integrability without external components. It has been designed to obtain a basic efficient block for fuzzy processing, to be included in a future architecture.