• The Journal of the Acoustical Society of Korea
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• v.30 no.3
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• pp.115-122
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• 2011

In this paper, we present a method to estimate an accurate real-time sound source direction based on time delay of arrival by using generalized cross correlation with four cross-type microphones. In general, existing systems have two disadvantages such as system embedding limitation due to the necessity of data acquisition for signal processing from microphone input, and real-time processing difficulty because of the increased number of channels for sound direction estimation using DSP processors. To cope with these disadvantages, the system considered in this paper proposes hardware design for enhanced real-time processing using microphone array signal processing. An accurate direction estimation and its design time reduction is achieved by means of an efficient hardware design using spatial segmentation methods and verification techniques. Finally we develop a system which can be used for embedded systems using a sound codec and an FPGA chip. According to experimental results, the system gives much faster real-time processing time compared with either PC-based systems or the case with DSP processors.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.249-256
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• 2007

AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.10 no.3
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• pp.237-242
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• 2016

The major advantage of slip-ring technology in Spiral CT is that it facilitates continuous rotation of the x-ray tube, so that volume data can be acquired from a patient quickly. Not only for such a fast scan, but also for the dose reduction purpose, high signal-to-noise ratio and fast data acquisition system is required. In this study, we have built a multi-channel photodetector and multi-channel data acquisition system for CT application. The detector module consisted of CdWO4 crystal and Si photodiode in 16 channels. For the performance test of the preamplifier stage, both the transimpedance and switched integrator types are optimized for the photodetector modules. Switched integrator showed better noise performance in the limited bandwidth which is suitable for the current CT application. The control sequence for data acquisition and 20 bit ADC is designed with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and implemented on FPGA(Field Programmable Gate Array) chip. Our Si photodiode detector module coupled to CdWO4 crystal showed comparable signal with other commercially available photodiode for CT. Switched integrator type showed higher SNR but narrower bandwidth compared to transimpedance preamplifier. Digital hardware is designed by FPGA, so that the control signal could be redesigned without hardware alteration.