• Nuclear Engineering and Technology
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• 제55권8호
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제5권7호
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권11호
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• 제57권4호
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• pp.356-361
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• 2008

The conventional drive system of SRM has a current sensor per each phase. The torque demand signal generated by the outer control loop is translated into individual current reference signal for each phase. The torque is controlled by regulating these currents. Using the SRM in a variable-speed control, the phase currents are generally regulated to achieve a square wave. The simplest form of current regulation uses fixed frequency delta modulation of the phase voltages. The aim of this paper is to regulate 3-phases current of SRM by only single current sensor using delta modulation with digital chip. In this paper, the asymmetric bridge converter which is able to control independently phases and be excited simultaneously is used as the driver system for 6/4 poles SRM. And the current sensor is replaced 3 sensors of each phase with only one on bus line of converter so as to detect current of every phase. The proposed delta modulation technique has been implemented in a simple digital logic circuit using EPLD(Electrically Programmable Logic Device). This method is verified through simulation and experiment results.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제18권9호
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• pp.2109-2116
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• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• Journal of the Korean Institute of Intelligent Systems
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• 제21권5호
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• pp.595-601
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• 2011

This paper presents balancing control of inverted pendulum on the ROBOKER arm using visual information. The angle of the inverted pendulum placed on the robot arm is detected by a stereo camera and the detected angle is used as a feedback and tracking error for the controller. Thus, the overall closed loop forms a visual servoing control task. To improve control performance, neural network is introduced to compensate for uncertainties. The learning algorithm of radial basis function(RBF) network is performed by the digital signal controller which is designed to calculate floating format data and embedded on a field programmable gate array(FPGA) chip. Experimental studies are conducted to confirm the performance of the overall system implementation.

• Journal of Advanced Navigation Technology
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• 제19권5호
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• Journal of the Korea Society of Computer and Information
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• 제23권1호
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• pp.33-39
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• 2018

In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

• The Transactions of the Korea Information Processing Society
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• 제6권7호
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• pp.1929-1940
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• 1999

In this paper a VLSI design for the automatic magnetizing and inspection system has been presented. This is a design of a peripheral controller, which magnetizes CRTs and computer monitors and controls the automatic inspection system. We implemented a programmable peripheral interface(PPI) circuit of the control and protocol module for the magnetizer controller by using a 0.8um CMOS SOG technology of ETRI. Most of the PPI functions have been confirmed. In the conventional method, the propagation/ramp delay model was used to predict the delay of cells, but used to model on only a single cell. Later, a modified "linear delay predict model" was suggested in the LODECAP(LOgic DEsign CAPture) by adding some factors to the prior model. But this has not a full model on the delay chain. In this paper a new " delay predict equation" for the design of the timing control block in PPI system has been suggested. We have described the detail method on a design of delay chain block according to the extracted equation and applied this method to the timing control block design. And we had descriptions on the other blocks of this system.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제35권1C호
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• pp.24-32
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• 2010

In this paper we proposed an object tracking system that detects the abandoned and removed objects, which is to be used in the intelligent surveillance applications. After the GMM based background subtraction and by using histogram method, the static region is identified to detect abandoned and removed objects. Since the system is implemented on DSP chip, it operates in realtime and is programmable. The input videos used in the experiment contain various indoor and outdoor scenes, and they are categorized into three different complexities; low, midium and high. By 10 times of experiment, we obtained high detection ratio at low and medium complexity sequences. On the high complexity video, successful detection ratio was relatively low because the scene contains crowdedness and repeated occlusion. In the future work, these complicated situation should be solved.