• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.464-466
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• 2019

Controllers used in nuclear power plants require high reliability. A controller including a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (referred to hereinafter as FPGA) has been applied to many Nuclear Power Plants (NPP) in the past, including the APR1400 (Advanced Power Reactor 1400), a Korean digital nuclear power plant. Initially, the FPGA was considered as a general IC (Integrated Circuit) and verified only by device verification and performance testing. In the 1990s, research on FPGA verification began, and until the FPGA became a chip, it was regarded as software and the software Verification and Validation (V&V) using IEEE 1012-2004 was implemented. Currently, IEC 62566, which is a European standard, has been applied for a lot of verification. This method has been evaluated as the most sensible method to date. This is because the method of verifying the characteristics of SoC (System on Chip), which has been a problem in the existing verification method, is sufficiently applied. However, IEC 62566 is a European standard that has not yet been adopted in the United States and maintains the application of IEEE 1012 for FPGA. IEEE 1012-2004 or IEC 62566 is a technical standard. In practice, various methods are applied to meet technical standards. In this paper, we describe the procedure and important points of verification method of Nuclear Safety Class FPGA applying SoC verification method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of IKEEE
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• v.17 no.3
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• pp.241-247
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• 2013

This paper presents the design of a System on Programmable Chip (SoPC) based on Field Programmable Gate Array (FPGA) for speech recognition in which Mel-Frequency Cepstral Coefficients (MFCC) for speech feature extraction and Vector Quantization for recognition are used. The implementing process of the speech recognition system undergoes the following steps: feature extraction, training codebook, recognition. In the first step of feature extraction, the input voice data will be transformed into spectral components and extracted to get the main features by using MFCC algorithm. In the recognition step, the obtained spectral features from the first step will be processed and compared with the trained components. The Vector Quantization (VQ) is applied in this step. In our experiment, Altera's DE2 board with Cyclone II FPGA is used to implement the recognition system which can recognize 64 words. The execution speed of the blocks in the speech recognition system is surveyed by calculating the number of clock cycles while executing each block. The recognition accuracies are also measured in different parameters of the system. These results in execution speed and recognition accuracy could help the designer to choose the best configurations in speech recognition on SoPC.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.1
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• pp.73-80
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• 2004

We have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers and GUI are implemented as a system-on-chip for multi-axis motion control. Comparing with the commercial motion controller LM 629, since it has multi-independent PID controllers, we have several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, motion of the robot hand is controlled. The robot hand has three fingers with 2 joints each. Finger movements show that tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.89-97
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• 2008

Chaotic behavior in motor systems is undesired dynamics in real-time implementation since the speed is oscillated in a wide range and the torque is changed by a random manner. We present an adaptive control approach for time-varying permanent-magnet synchronous motors (PMSM) with chaotic phenomenon. We consider that its parameters are changed randomly within certain bounds. First, a nonlinear system model of a PMSM is transformed to derive a nominal linear control strategy. Then, an auxiliary control for compensating real-time control error occurred by system perturbation due to parameter change is designed by using Lyapunov stability theory. Numerical simulation is accomplished for evaluating its efficiency and reliability comparing with the traditional control method. Additionally, we test our control method in real-time motor experiment including a PSoC based drive system to demonstrate its practical applicability.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.76-79
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• 2004

The DS-SS (Direct Sequence Spread Spec1nun) transmitter is part of a low data rate (∼150 kbps - burst rate and 64 bps - average data rate) wireless communication system. It is traditionally implemented using Digital Signal processing chip (DSP). However, with rapid increase in variety of services through cell phones, such as, web access, video transfer, online games etc. demand for higher rate is increasing steadily. Since the chip rate and thereby the sampling rate requirements of the system are fairly high, the transmitter should implemented using Field programmable Gate Arrays FPGAs instead of a DSP. This paper shows the steps taken to get a working prototype of the transmitter unit on a FPGA based platform.

• Journal of information and communication convergence engineering
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• v.15 no.3
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• pp.151-159
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• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.11a
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.