• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.23-32
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• 2012

There is a method which identifies validity of program by transforming program to verification condition to verify program. If program is verified by generating verification condition, verification condition must have enough and accurate information for verifying program. However, verification condition is consisting of logical formulas, so the user cannot easily identify the verification condition. In this paper, we implemented program that visualize the poorly readable verification conditions. By the program, the users can easily identify information, such as the relationship between logical formulas that represent verification condition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.6
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• pp.521-524
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• 2005

This paper is the study on verification when there is a conflict fur degree of software completion. Therefore, in this paper, we propose an weight setting method and show the degree fur importance of each function to obtain the independence for verification. Eventually, we adapted the proposed contents to the specific verification event.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.2
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• pp.29-37
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• 2011

Java bytecode verification is a critical process to guarantee the safety of transmitted Java applet on the web or contemporary embedded devices. We propose a design of framework which enables to analyze and verify java bytecode. The designed framework translates from a java bytecode into the intermediate representation which can specify a properties of program without using an operand stack. Using the framework is able to produce automatically error specifications that could be occurred in a program and express specifications annotated in intermediate representation by a user. Furthermore we design a verification condition generator which converts from an intermediate representation to a verification condition, a verification engine which verifies verification conditions from verification condition generator, and a result reporter which displays results of verification.

• Journal of the Korea Safety Management & Science
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• v.17 no.1
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• pp.179-192
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• 2015

In an automated industry PLC plays a central role to control the automation system. Therefore, fault free operation of PLC controlled automation system is essential in order to maximize a firm's productivity. A prior test of control system is a practical way to check fault operations, but it is a time consuming job and can not check all possible fault operation. A formal verification of PLC program could be a best way to check all possible fault situation. Tracing the history of the study on formal verification, we found three problems, the first is that a formal representation of PLC control system is incomplete, the second is a state explosion problem and the third is that the verification result is difficult to use for the correction of control program. In this paper, we propose a transformation method to reproduce the control system correctly in formal model and efficient procedure to verify and correct the control program using verification result. To demonstrate the proposed method, we provided a suitable case study of an automation system.

• 시스템엔지니어링워크숍
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• s.6
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• pp.126-129
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• 2005

Systems engineering requirement verification model developmetn for High Speed Railway systems in progress is a national large system development program that is not only large-size and complex but also multi-disciplinary in nature. For the High Speed Railway TEP development, verification requirements that could verify system function, performance, and constraint, should be derived from SSS(system Segment specification). Hereafter, this could be referred to as verification requirements. System engineering process establishes traceability between verification requirements and system requirements. These tasks could be accomplished by the schema. using computer-aided Systems Engineering tool(CORE), High Speed Railway program can become a database and other system related to High Speed Railway program will be developed effectively and efficiently.

• KIPS Transactions on Software and Data Engineering
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• v.4 no.1
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• pp.1-8
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• 2015

Safety critical systems require exhaustive verification of safety properties, because even a single corner-case fault can cause a critical safety failure. However, existing verification approaches are too costly in terms of time and computational resource required, making it hard to be applied in practice. In this paper, we implemented a tool for minimizing the size of the verification target w.r.t. verification properties to check, based on program slicing technique[1]. The efficacy of program slicing using our tool is demonstrated in a case study with a verification target Trampoline[3], which is an open source automotive operating system compliant with OSEK/VDX[2]. Experiments have shown enhanced performance in verification, with a 71% reduction in the size of the code.

• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.61-69
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• 2012

BIRS is an intermediate representation for verifying Java program. Java program in the form of bytecode could be translated into BIRS code. Verification conditions are generated from the BIRS code to verify the program. We propose a method generating verification conditions for BIRS code. Generating verification conditions is composed of constructing control flow graph for BIRS code, depth first searching for the control flow graph to generate basic paths, and calculating weakest preconditions of the basic paths.

• Journal of Korean Elementary Science Education
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• v.34 no.1
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• pp.95-108
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• 2015

Studies showed that elementary school students had difficulties in the idea generation for creative problem solving, and they were also not to go through with the verification process for selecting idea. Thus, it may be more effective to provide an actualized idea generation and verification methods. In this study, we developed the creativity problem solving program with the attribute listing and PMI skills in the idea generation and verification stages respectively and applied it to six groups consisting of 5th elementary school students. We analyzed the creativity and the verbal interactions among the students at the level of interaction units. The analyses of the results revealed that the problem solving program with the creative thinking skills had significant effects on the fluency and originality that were sub-elements consisting creativity. In the analyses of interaction unit, the frequencies of the 'making suggestion' at the idea generation stage were high. And at the idea verification stage, the frequencies of the 'making suggestion' and 'receiving opinion' were high. Educational implications of these findings were discussed.

• 수도
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• v.24 no.5 s.86
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• pp.16-28
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• 1997

As sewerage works has become one of the major public works in Korea, the employment of advanced and more appropriate sewerage technology has become essential to improve the efficiency of sewerage works. During last 10 years, the Korean Government has made tremendous amount of investment on sewerage works so that treatment plants in 58 cities have treatment capacity which is equivalent to 52.8% of total daily sewage generation in Korea. This remarkable development, however, has heavily depended on one technology, the conventional activated sludge process as more than 95% of the existing plants employ this process, Recently, the Korean Government and local authorities have plans to introduce more appropriate sewage treatment technologies and research and development in this area has become very active. To encourage employing new and appropriate technologies, however, the proper technology evaluation and verification program for new process is needed. The public sector should play a key role in this program since the sewerage works is one of the major public works. In this paper, the technology evaluation and verification programs related with sewerage facilities in the US and Japan are briefly reviewed. The Innovatived and Alternative Technology programs which was operated by US EPA until recently and Environmental Technology Verification(ETV) program which was commenced in 1995 are introduced. The technology verification programs operated in Japan and also in Korea are also reviewed in this paper to propose a future direction for development of the appropriate evaluation and verification system.

• The KIPS Transactions:PartD
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• v.12D no.7 s.103
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• pp.931-936
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• 2005

There may be subtle errors in embedded software since its functionality is very complex. Thus formal verification for detecting them is very needed. Model checking is one of formal verification techniques, and SLAM is a well-known software model checking tool for verifying safety properties of embedded C program. In this paper, we develop a software model checker like SLAM for verifying embedded Java program Compared to SLAM, our tool allows to verify liveness properties as well as safety ones. As a result, we verify some desired properties in embedded Java program for controlling REGO robot.