• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.1-10
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• 1994

In this paper, we propose a processor allocation algorithm using the PGG(Packed Gray code Group) for the MIMD hypercube. The number of k-D subcubes in an n-cube is C(n.k) en-k. When the PGG is employed in the processor allocation, C(n, k) PGG's are required to recognize all the k-D subcubes in an n-cube. from the simulation we find that the capability of processor allocation using only 40% of C(n, k) PGG's is about the same as that of the allocation using all the PGG's.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.168-176
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• 1996

This paper presetns a 2-D DCT architecture adopting accurac y compensator for reducing the hardware complexity and increasing processing speed in VL\ulcornerSI implementation. In the application fields such as moving pictures experts group (MPEG) and joint photographic experts group (JPEG), 2-D DCT processor must be implemented precisely enough to meet the accuracy specifications of the ITU-T H.261. Almost all of 2-D DCT processors have been implemented using many multiplications and accumulations of matrices and vectors. The number of multiplications and accumulations seriously influence on comlexity and speed of 20D DCT processor. In 2-D DCT with fixed-point calculations, the computation bit width must be sufficiently large for the above accuracy specifications. It makes the reduction of hardware complexity hard. This paper proposes the accuracy compensator which compensates the accuracy of the finite word length calculation. 2-D DCT processor with the proposed accuracy compensator shows fairly reduced hardware complexity and improved processing speed.

• ETRI Journal
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• v.31 no.6
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• pp.709-716
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• 2009

In this paper, we propose a novel reconfigurable processor using dynamically partitioned single-instruction multiple-data (DP-SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P-SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD-based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P-SIMD, and DP-SIMD. Experimental results show that the DP-SIMD control method is more efficient than SIMD and P-SIMD control methods by about 15% and 14%, respectively.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2578-2580
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• 1999

In this paper, an embedded micro processor based resistance spot welding controller is introduced which has been recently developed by Hyosung Co. Ltd. The performance of rapid and constant high current control is tested experimentally. This paper shows configurations of measuring system for high current and realtime RMS conversion techniques of sampled discrete data. A digital proportional control is adopted for this system and the result shows that this new product is working well at wide range of welding current and the performance is improved compared with some other commercially available controllers that are widely used in our industries. User friendly MMI system and a computer network system to monitor each welding processes are also presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.234-239
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• 2006

In the past decade, several tools have been developed to automate the floating-point to fixed-point conversion for DSP systems. In the conversion process, a number of scaling shifts are introduced, and they inevitably alter the original code sequence. Recently, we have observed that a compiler can often be adversely affected by this alteration, and consequently fails to generate efficient machine code for its target processor. In this paper, we present an optimization technique that safely migrates scaling shifts to other places within the code so that the compiler can produce better-quality code. We consider our technique to be safe in that it does not introduce new overflows, yet preserving the original SQNR. The experiments on a commercial fixed-point DSP processor exhibit that our technique is effective enough to achieve tangible improvement on code size and speed for a set of benchmarks.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.5
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• pp.116-123
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• 2000

This paper presents an NC code post-processor that adjusts feedrates to keep the variation of metal removal rate along the tool paths minimum. Metal removal rate is estimated by virtually machining the part, whose surface model is built from a series of NC codes defined in operation plan, with cutting-tool-assembly models, whose geometry are defined in a machining database. The NC code post-processor modifies the feedrates by the adjustment rules, which are based on the machining knowledge for effective machining. This paper illustrates a procedure fur grouping machining conditions and we also show how to determine an adjustment rule for a machining-condition group. An example part was machined and it shows that the variation of cutting force was dramatically reduced after applying the NC code post-processor. The NC code post-processor is expected to increase productivity while maintaining the quality of the machined part.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.1
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• pp.119-127
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• 2012

This paper describes development and performance test of signal processor for the millimeter wave seeker. A ground to air guidance missile is required various beam patterns in order to counteract different kind of target. Therefore, we designed the hardware and software architecture considering flexibility. This signal processor consists of ADC, FPGA, DSP and etc. FPGA provides peripheral interface to DSP and convert digital IF signal to baseband signal. DSP performs signal processing, calculates target's information and controls devices. Each parts' hardware are connected in series and signal processing algorithms for various beam patterns are built in parallel.

• Journal of IKEEE
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• v.21 no.1
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• pp.77-80
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• 2017

In this paper, we proposed a way to improve performance of GP-GPU by deletion of superscalar issue from its original form. At first, we simplified the structure of stream processor in order to eliminate superscalar issue. Under this condition, preservation of hardware size and increasing of thread number were followed by functional improvement of GP-GPU. As the number of thread was getting larger, we proposed the new model of warp scheduler which adjusts the group of thread. This superscalar issue-deleted warp scheduler transferred the instructions to warp which was activated by Round Robin Scheduling. Performance comparison was conducted by Gaussian filtering and the results indicated that our newly designed GP-GPU showing 7.89 times better in its performance than original one.