• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.510-513
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• 1988

This paper describes an effective trunk loop signal processing method and analyzes execution time of program in the DTCP(Digital Trunk Circuit Processor) in the TDX-1A digital switching system. To predict a maximum trunk capacity, also analyzes to Z80A system clock(4Mbit/s, 2.5Mbit/s) and scanning period(8mS,5mS) respectively.

• Nuclear Engineering and Technology
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• v.53 no.2
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• pp.688-694
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• 2021

The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues. The closed-loop stability of the controller-plant structure is established. Further, the designed PI/PD controllers are implemented in real-time on a DSP processor. The simulation and real-time hardware studies confirm that the designed PI/PD controllers result in a damped stable closed-loop response.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.10
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• pp.863-871
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• 2017

LMS (least mean square) algorithm widely used in the AVCS (active vibration control system) of helicopters calculates control input using the forward path transfer function and error signal. If the error signal is sinusoidal, it can be represented as the combination of cosine and sine functions with frequency and phase synchronized with the reference signal. The control input also has the same frequency, therefore control algorithm can be simply implemented if the cosine and the sine amplitudes of the control input are calculated and the frequency and phase of the reference signal are used. Calculation of the control input is implemented as simple matrix operation and the change of the control command is slower than the frequency of the error signal, consequently control algorithm can be operated at lower frequency. The signal processing algorithm extracting cosine and sine components of the error signals are modeled using Simulink and PIL (processor-in-the-loop) mode simulation was executed for real-time performance evaluation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.559-564
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• 2014

A microgrid as a small scale power system is operated by the grid-connected mode and islanded mode. It is anticipated that the battery energy storage system (BESS) is able to be applied to the microgrid for stable power control, such as tie-line and smoothing control in the grid-connected mode and voltage and frequency control in the islanded mode. In this paper, a digital signal processor (DSP), Two BESS controllers based on TMS320F28335 of a microgrid are implemented and are tested to show control performance in the hardware-in-the loop simulation (HILS) system.

• Journal of Power Electronics
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• v.11 no.2
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.91-102
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• 2005

Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1025-1035
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• 2016

Luenberger observer (LO)-based sensorless multi-loop control of a converter requires an iterative trial-and-error design process, considering that many parameters should be determined, and loop gains are indirectly related to the closed-loop characteristics. Robust H∞ control adopts a compact sensorless controller. The algebraic Riccati equation (ARE)-based and linear matrix inequality (LMI)-based H∞ approaches need an exhaustive procedure, particularly for a low-order controller. Therefore, in this study, a novel robust H∞ synthesis approach is proposed to design a low-order sensorless controller for boost converters, which need not solve any ARE or LMI, and to parameterize the controller by an adjustable parameter behaving like a "knob" on the closed-loop characteristics. Simulation results show the straightforward closed-loop characteristics evaluation and better dynamic performance by the proposed H∞ approach, compared with the LO-based sensorless multi-loop control. Practical experiments on a digital processor confirmed the simulation results.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.9
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• pp.72-79
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• 2004

A method for thruster fault diagnosis for launch vehicle upper stage was developed. In order to protect the launch vehicle against the occurrence of faults, it is necessary to detect and identify the fault, as well as to reconfigure the controller of the vehicle. Considering the upper stage launch vehicle using reaction control system, an analytical method was adopted in order to detect the fault occurred in thruster. The fault detection scheme can be applied to the system regardless of the form of thruster fault occurred - leakage or lock-out. Results from processor-in-the-loop simulation are provided to demonstrate the validity of this fault detection and isolation scheme for the upper stage launch vehicle.